Message ID | 20231022232932.80507-36-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show
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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k26-20020a63ba1a000000b005b25a04cf8bsm4023772pgf.12.2023.10.22.16.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 16:30:03 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v5 35/94] target/sparc: Move MULX to decodetree Date: Sun, 22 Oct 2023 16:28:33 -0700 Message-Id: <20231022232932.80507-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022232932.80507-1-richard.henderson@linaro.org> References: <20231022232932.80507-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org |
Series |
target/sparc: Convert to decodetree
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expand
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diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1cff18fa1f..1a04a8e229 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -31,6 +31,7 @@ CALL 01 i:s30 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc +@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 { [ @@ -165,6 +166,8 @@ ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc +MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d27876084e..20c59b6aaf 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4073,6 +4073,7 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, void (*func_cc)(TCGv, TCGv, TCGv)) { if (a->cc) { + assert(cc_op >= 0); return do_arith_int(dc, a, cc_op, func_cc, NULL); } return do_arith_int(dc, a, cc_op, func, funci); @@ -4090,6 +4091,7 @@ TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl) TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) +TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL) static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { @@ -4561,11 +4563,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0x9: /* V9 mulx */ - tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); - break; -#endif case 0xa: /* umul */ CHECK_IU_FEATURE(dc, MUL); gen_op_umul(cpu_dst, cpu_src1, cpu_src2);