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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k26-20020a63ba1a000000b005b25a04cf8bsm4023772pgf.12.2023.10.22.16.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 16:29:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v5 30/94] target/sparc: Remove cpu_wim Date: Sun, 22 Oct 2023 16:28:28 -0700 Message-Id: <20231022232932.80507-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022232932.80507-1-richard.henderson@linaro.org> References: <20231022232932.80507-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d87c08c18c..096cbb869f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -84,9 +84,7 @@ static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; -# define cpu_wim ({ qemu_build_not_reached(); (TCGv)NULL; }) #else -static TCGv cpu_wim; # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) @@ -103,8 +101,10 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; #define env_field_offsetof(X) offsetof(CPUSPARCState, X) #ifdef TARGET_SPARC64 +# define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) # define env64_field_offsetof(X) env_field_offsetof(X) #else +# define env32_field_offsetof(X) env_field_offsetof(X) # define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) #endif @@ -3414,7 +3414,8 @@ TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, static TCGv do_rdwim(DisasContext *dc, TCGv dst) { - return cpu_wim; + tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim)); + return dst; } TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim) @@ -3767,7 +3768,10 @@ TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr) static void do_wrwim(DisasContext *dc, TCGv src) { target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows); - tcg_gen_andi_tl(cpu_wim, src, mask); + TCGv tmp = tcg_temp_new(); + + tcg_gen_andi_tl(tmp, src, mask); + tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim)); } TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim) @@ -5939,8 +5943,6 @@ void sparc_tcg_init(void) #ifdef TARGET_SPARC64 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, -#else - { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" }, #endif { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },