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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:44:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 31/65] target/hppa: Decode d for unit instructions Date: Fri, 20 Oct 2023 13:42:57 -0700 Message-Id: <20231020204331.139847-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 14 +++++++------- target/hppa/translate.c | 25 ++++++++++++------------- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 26ca9f1063..03b1a11cac 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -59,7 +59,7 @@ # All insns that need to form a virtual address should use this set. &ldst t b x disp sp m scale size -&rr_cf t r cf +&rr_cf_d t r cf d &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh @@ -72,7 +72,7 @@ # Format definitions #### -@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf +@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @@ -156,13 +156,13 @@ andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d -uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf +uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf -uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf -uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf -dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf -dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf +uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d +uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d +dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d +dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 733d5fe067..c08156772a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1423,12 +1423,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, } static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool is_tc, + TCGv_reg in2, unsigned cf, bool d, bool is_tc, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest; DisasCond cond; - bool d = false; if (cf == 0) { dest = dest_gpr(ctx, rt); @@ -2751,7 +2750,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) return nullify_end(ctx); } -static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; @@ -2760,11 +2759,11 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) } tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg); return nullify_end(ctx); } -static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) +static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { TCGv_reg tcg_r1, tcg_r2, tmp; @@ -2775,21 +2774,21 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) tcg_r2 = load_gpr(ctx, a->r2); tmp = tcg_temp_new(); tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); return nullify_end(ctx); } -static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, false); } -static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, true); } -static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) +static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) { TCGv_reg tmp; @@ -2800,19 +2799,19 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) if (!is_i) { tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); tcg_gen_muli_reg(tmp, tmp, 6); - do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, + do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); return nullify_end(ctx); } -static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, false); } -static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, true); }