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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id m14-20020a50ef0e000000b0053f0e4e0411sm1747279eds.76.2023.10.20.09.37.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , Bin Meng , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 07/19] cpus: Filter for target specific CPU (riscv) Date: Fri, 20 Oct 2023 18:36:29 +0200 Message-ID: <20231020163643.86105-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Enforce qemu_get_cpu() to return RISCV CPUs in RISCV specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_RISCV_CPU) Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/sifive_plic.c | 2 +- hw/riscv/boot.c | 2 +- hw/riscv/opentitan.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 3e2534ac04..ea0e7af16e 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, for (i = 0; i < plic->num_addrs; i++) { int cpu_num = plic->addr_config[i].hartid; - CPUState *cpu = qemu_get_cpu(cpu_num, NULL); + CPUState *cpu = qemu_get_cpu(cpu_num, TYPE_RISCV_CPU); if (plic->addr_config[i].mode == PLICMode_M) { qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ea733b3df1..1d004660d4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count) int i; for (i = 0; i < hart_count; i++) { - CPUState *cs = qemu_get_cpu(i, NULL); + CPUState *cs = qemu_get_cpu(i, TYPE_RISCV_CPU); CPURISCVState *env = &RISCV_CPU(cs)->env; if (kvm_enabled()) { diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e98361de19..106ef5d2d0 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); for (i = 0; i < ms->smp.cpus; i++) { - CPUState *cpu = qemu_get_cpu(i, NULL); + CPUState *cpu = qemu_get_cpu(i, TYPE_RISCV_CPU); qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); @@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); qdev_connect_gpio_out(DEVICE(&s->timer), 0, - qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)), + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, TYPE_RISCV_CPU)), IRQ_M_TIMER)); /* SPI-Hosts */