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Wed, 18 Oct 2023 23:57:16 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([2401:4900:5302:9b99:4f57:4dc3:993d:4317]) by smtp.googlemail.com with ESMTPSA id k15-20020aa7998f000000b00690bd3c0723sm4507288pfh.99.2023.10.18.23.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 23:57:16 -0700 (PDT) From: Mayuresh Chitale To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Mayuresh Chitale , Alistair Francis Subject: [PATCH v3] target/riscv: pmp: Ignore writes when RW=01 Date: Thu, 19 Oct 2023 12:27:05 +0530 Message-Id: <20231019065705.1431868-1-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=mchitale@ventanamicro.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org As per the Priv spec: "The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved." However currently such writes are not ignored as ought to be. The combinations with RW=01 are allowed only when the Smepmp extension is enabled and mseccfg.MML is set. Signed-off-by: Mayuresh Chitale Reviewed-by: Alistair Francis --- Changes in v3: ==== - Rebase on latest riscv-to-apply.next - Add reviewed-by Changes in v2: ==== - Default RW to 00 in case of an illegal value target/riscv/pmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4dfaa28fce2..162e88a90a6 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -123,6 +123,11 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (locked) { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n"); } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) { + /* If !mseccfg.MML then ignore writes with encoding RW=01 */ + if ((val & PMP_WRITE) && !(val & PMP_READ) && + !MSECCFG_MML_ISSET(env)) { + val &= ~(PMP_WRITE | PMP_READ); + } env->pmp_state.pmp[pmp_index].cfg_reg = val; pmp_update_rule_addr(env, pmp_index); return true;