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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:52:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 30/61] target/hppa: Decode d for logical instructions Date: Wed, 18 Oct 2023 14:51:04 -0700 Message-Id: <20231018215135.1561375-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++---- target/hppa/translate.c | 15 +++++++-------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index aebe03ccfd..26ca9f1063 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -61,6 +61,7 @@ &rr_cf t r cf &rrr_cf t r1 r2 cf +&rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf @@ -73,6 +74,7 @@ @rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 @@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5 # Arith/Log #### -andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf -and 000010 ..... ..... .... 001000 - ..... @rrr_cf -or 000010 ..... ..... .... 001001 - ..... @rrr_cf -xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf +andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d +and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d +or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d +xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 94969cf2f0..5eecced442 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1392,11 +1392,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, } static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, + TCGv_reg in2, unsigned cf, bool d, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest = dest_gpr(ctx, rt); - bool d = false; /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1409,7 +1408,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, } } -static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg tcg_r1, tcg_r2; @@ -1419,7 +1418,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, } tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); + do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); return nullify_end(ctx); } @@ -2672,17 +2671,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) return do_sub_reg(ctx, a, true, true, false); } -static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_andc_reg); } -static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_and_reg); } -static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) { if (a->cf == 0) { unsigned r2 = a->r2; @@ -2734,7 +2733,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) return do_log_reg(ctx, a, tcg_gen_or_reg); } -static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_xor_reg); }