From patchwork Tue Oct 17 23:03:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nabih Estefan X-Patchwork-Id: 1850535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20230601 header.b=U6SBgGL3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S98jx6VKWz23kM for ; Wed, 18 Oct 2023 10:06:29 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qst6g-0006Ni-83; Tue, 17 Oct 2023 19:04:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <34BIvZQwKCvEgTUbaXlmXYTgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--nabihestefan.bounces.google.com>) id 1qst6e-0006MX-P1 for qemu-devel@nongnu.org; Tue, 17 Oct 2023 19:04:08 -0400 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <34BIvZQwKCvEgTUbaXlmXYTgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--nabihestefan.bounces.google.com>) id 1qst6X-0002Jk-S2 for qemu-devel@nongnu.org; Tue, 17 Oct 2023 19:04:08 -0400 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-d9a397a7c1cso8619623276.2 for ; Tue, 17 Oct 2023 16:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1697583840; x=1698188640; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=xVjSz03YhlqWn4x5rMD+S7ZjWNLMHmSXRcMSJqLVbbo=; b=U6SBgGL3Fp0iFxrpQljWW9VC6TWaxMhrKDzqG5ahf9fX/PAkfukNFSUqnPSxbh5vBv Q+DAc+QkJPRjvAEcfZyg/0ITtyvbkfyuemeMdFPfs2HLII5e/c5mSiC3fCUIfK5/FQbz BBCH1jgwUrxbYj9NfadMuVzzAItecIVVWA73X1Ic9+YAO65hj/o2OW7hvwhE4rNBqc9+ aXUqbE/BZQ+Ng7wkNSzq3TGNf2ZXSrHTvbtkDeGQs0tvJMMUkW50tvMcRiOm9Kg8xiui 4vL26rhxLUohjV5WdJW75g9UUKKJ8fQWEEfg8W23CafLKg2aYeNBofAcr83Gd6zgxjQ6 bjgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697583840; x=1698188640; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xVjSz03YhlqWn4x5rMD+S7ZjWNLMHmSXRcMSJqLVbbo=; b=XYVQGEZYte+LIQnhU2zRrsbzjdtU8vZ/KqFwuAjG14N9U6hIIp9O+H5wQmDfAMByvz PboVa/X9EgIbUjDgBq96biDscHhSiy27Ql0D+3sGLf9kAtME+EqamRWWo1vOe11LLspW OJSSLcQZuvsGgkgTWavCMen7Q7VZ/Bn0F9iFhKN/0mqA0qZMpsl2CJZxd7+KjeSYAnQ7 Uq92Kz09vldGecGE+MEF+1c+jeKk9t21ZEOOrp9v41VQwicW62P+P8meMoOFuUV1G2Ko d5iCUuhgW6b2j9KlDIY8YBA1f82hAaq0p1VoPHLw58s60r1JTuXuZrKHlquEXtjxBPWf Foog== X-Gm-Message-State: AOJu0Ywc995Goa3UFYR6xwgMx1juHwtjSAMSjGT0V6eVyRs8h4CiXBRn REOoh336xALSI6ZcenozX87JTLCbVMEqclcoaC8= X-Google-Smtp-Source: AGHT+IFnNHnenDzbPDX4a6CaIIKeibks5F/TjxUk31vhgEjYJ8Xlcm64wese0+7vkiEBsKOBgpFWSk0MPaZk+2B8ALY= X-Received: from nabihestefan.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:2737]) (user=nabihestefan job=sendgmr) by 2002:a05:6902:1825:b0:d9a:c3a2:48a3 with SMTP id cf37-20020a056902182500b00d9ac3a248a3mr73028ybb.6.1697583840239; Tue, 17 Oct 2023 16:04:00 -0700 (PDT) Date: Tue, 17 Oct 2023 23:03:36 +0000 In-Reply-To: <20231017230342.311227-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20231017230342.311227-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.655.g421f12c284-goog Message-ID: <20231017230342.311227-6-nabihestefan@google.com> Subject: [PATCH v3 05/11] hw/arm: Add GMAC devices to NPCM7XX SoC From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, avi.fishman@nuvoton.com Received-SPF: pass client-ip=2607:f8b0:4864:20::b4a; envelope-from=34BIvZQwKCvEgTUbaXlmXYTgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb4a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Hao Wu Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 36 ++++++++++++++++++++++++++++++++++-- include/hw/arm/npcm7xx.h | 2 ++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c9e87162cb..12e11250e1 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -91,6 +91,7 @@ enum NPCM7xxInterrupt { NPCM7XX_GMAC1_IRQ = 14, NPCM7XX_EMC1RX_IRQ = 15, NPCM7XX_EMC1TX_IRQ, + NPCM7XX_GMAC2_IRQ, NPCM7XX_MMC_IRQ = 26, NPCM7XX_PSPI2_IRQ = 28, NPCM7XX_PSPI1_IRQ = 31, @@ -234,6 +235,12 @@ static const hwaddr npcm7xx_pspi_addr[] = { 0xf0201000, }; +/* Register base address for each GMAC Module */ +static const hwaddr npcm7xx_gmac_addr[] = { + 0xf0802000, + 0xf0804000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -462,6 +469,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); } + for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { + object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC); + } + object_initialize_child(obj, "pci-mbox", &s->pci_mbox, TYPE_NPCM7XX_PCI_MBOX); object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); @@ -695,6 +706,29 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); } + /* + * GMAC Modules. Cannot fail. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) != ARRAY_SIZE(s->gmac)); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) != 2); + for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]); + + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]); + int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects * specified, but this is a programming error. @@ -765,8 +799,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); - create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); - create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index cec3792a2e..9e5cf639a2 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -30,6 +30,7 @@ #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/net/npcm7xx_emc.h" +#include "hw/net/npcm_gmac.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -105,6 +106,7 @@ struct NPCM7xxState { OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; NPCM7xxEMCState emc[2]; + NPCMGMACState gmac[2]; NPCM7xxPCIMBoxState pci_mbox; NPCM7xxSDHCIState mmc; NPCMPSPIState pspi[2];