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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jf4-20020a170903268400b001ca21e05c69sm629150plb.109.2023.10.16.23.13.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:13:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 35/90] target/sparc: Move UDIV, SDIV to decodetree Date: Mon, 16 Oct 2023 23:11:49 -0700 Message-Id: <20231017061244.681584-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017061244.681584-1-richard.henderson@linaro.org> References: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 66 ++++++++++++++++++++++----------------- 2 files changed, 41 insertions(+), 29 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a2512d8d47..7d1afb2a87 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -180,5 +180,9 @@ SUBC 10 ..... 001100 ..... . ............. @r_r_ri SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri UDIVX 10 ..... 001101 ..... . ............. @r_r_ri SDIVX 10 ..... 101101 ..... . ............. @r_r_ri +UDIV 10 ..... 001110 ..... . ............. @r_r_ri +UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri +SDIV 10 ..... 001111 ..... . ............. @r_r_ri +SDIVcc 10 ..... 011111 ..... . ............. @r_r_ri Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c2e4172872..d57df60170 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -655,6 +655,26 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) gen_helper_sdivx(dst, tcg_env, src1, src2); } +static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udiv(dst, tcg_env, src1, src2); +} + +static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdiv(dst, tcg_env, src1, src2); +} + +static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udiv_cc(dst, tcg_env, src1, src2); +} + +static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdiv_cc(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -2869,6 +2889,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) # define avail_64(C) false #endif #define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +#define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV) #define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) @@ -4166,6 +4187,17 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri *a, return do_cc_arith(dc, a, -1, func, funci); } +static bool do_flags_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op, + void (*func)(TCGv, TCGv, TCGv)) +{ + if (do_arith(dc, a, func, NULL)) { + /* Assume FUNC has set env->cc_op and all cc_foo variables. */ + dc->cc_op = cc_op; + return true; + } + return false; +} + static bool trans_OR(DisasContext *dc, arg_r_r_ri *a) { /* For simplicity, we under-decoded the rs2 form. */ @@ -4201,6 +4233,8 @@ TRANS(UMUL, MUL, do_arith, a, gen_op_umul, NULL) TRANS(SMUL, MUL, do_arith, a, gen_op_smul, NULL) TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL) TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL) +TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL) +TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4212,6 +4246,8 @@ TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) TRANS(UMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) TRANS(SMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) +TRANS(UDIVcc, DIV, do_flags_arith, a, CC_OP_DIV, gen_op_udivcc) +TRANS(SDIVcc, DIV, do_flags_arith, a, CC_OP_DIV, gen_op_sdivcc) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4695,35 +4731,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) #endif } else if (xop < 0x36) { if (xop < 0x20) { - cpu_src1 = get_src1(dc, insn); - cpu_src2 = get_src2(dc, insn); - switch (xop & ~0x10) { - case 0xe: /* udiv */ - CHECK_IU_FEATURE(dc, DIV); - if (xop & 0x10) { - gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op = CC_OP_DIV; - } else { - gen_helper_udiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - case 0xf: /* sdiv */ - CHECK_IU_FEATURE(dc, DIV); - if (xop & 0x10) { - gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op = CC_OP_DIV; - } else { - gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - default: - goto illegal_insn; - } - gen_store_gpr(dc, rd, cpu_dst); + goto illegal_insn; } else { cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn);