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envelope-from=kbastian@mail.uni-paderborn.de; helo=zuban.uni-paderborn.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Bastian Koppelmann --- configs/devices/tricore-softmmu/default.mak | 1 + docs/about/emulation.rst | 3 +++ qemu-options.hx | 3 ++- target/tricore/translate.c | 13 +++++++++++-- 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/configs/devices/tricore-softmmu/default.mak b/configs/devices/tricore-softmmu/default.mak index cb8fc286eb..883903073c 100644 --- a/configs/devices/tricore-softmmu/default.mak +++ b/configs/devices/tricore-softmmu/default.mak @@ -1,2 +1,3 @@ CONFIG_TRICORE_TESTBOARD=y CONFIG_TRIBOARD=y +CONFIG_SEMIHOSTING=y diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index 0ad0b86f0d..3ee90bd2aa 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -185,6 +185,9 @@ for that architecture. * - RISC-V - System and User-mode - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc + * - TriCore + - System + - Infineon ISS syscall handling (for GNU tools) * - Xtensa - System - Tensilica ISS SIMCALL diff --git a/qemu-options.hx b/qemu-options.hx index 54a7e94970..d7a6cb94c9 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4816,7 +4816,8 @@ ERST DEF("semihosting", 0, QEMU_OPTION_semihosting, "-semihosting semihosting mode\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | - QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) + QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV | + QEMU_ARCH_TRICORE) SRST ``-semihosting`` Enable :ref:`Semihosting` mode (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). diff --git a/target/tricore/translate.c b/target/tricore/translate.c index dd812ec0f0..1eb44c78c2 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -25,6 +25,7 @@ #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "qemu/qemu-print.h" +#include "semihosting/semihost.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -3151,6 +3152,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, } } +static void gen_debug(DisasContext *ctx) +{ + if (semihosting_enabled(false)) { + gen_helper_1arg(tricore_semihost, ctx->base.pc_next); + } else { + /* raise EXCP_DEBUG */ + } +} /* * Functions for decoding instructions @@ -3497,7 +3506,7 @@ static void decode_sr_system(DisasContext *ctx) ctx->base.is_jmp = DISAS_EXIT; break; case OPC2_16_SR_DEBUG: - /* raise EXCP_DEBUG */ + gen_debug(ctx); break; case OPC2_16_SR_FRET: gen_fret(ctx); @@ -7926,7 +7935,7 @@ static void decode_sys_interrupts(DisasContext *ctx) switch (op2) { case OPC2_32_SYS_DEBUG: - /* raise EXCP_DEBUG */ + gen_debug(ctx); break; case OPC2_32_SYS_DISABLE: if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {