@@ -179,3 +179,5 @@ UMUL 10 ..... 001010 ..... . ............. @r_r_ri
UMULcc 10 ..... 011010 ..... . ............. @r_r_ri
SMUL 10 ..... 001011 ..... . ............. @r_r_ri
SMULcc 10 ..... 011011 ..... . ............. @r_r_ri
+SUBC 10 ..... 001100 ..... . ............. @r_r_ri
+SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri
@@ -4201,6 +4201,30 @@ static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a)
return advance_pc(dc);
}
+static bool trans_SUBC(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, false);
+ return advance_pc(dc);
+}
+
+static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, true);
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4625,10 +4649,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0xc: /* subx, V9 subc */
- gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
- (xop & 0x10));
- break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 28 ++++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-)