@@ -78,3 +78,8 @@ RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
+
+{
+ FLUSHW 10 00000 101011 00000 0 0000000000000
+ RDTBR 10 rd:5 101011 00000 0 0000000000000
+}
@@ -3445,6 +3445,7 @@ static TCGv do_rdtba(DisasContext *dc, TCGv dst)
return cpu_tbr;
}
+TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba)
TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba)
static TCGv do_rdpstate(DisasContext *dc, TCGv dst)
@@ -3583,6 +3584,16 @@ static TCGv do_rdver(DisasContext *dc, TCGv dst)
TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver)
+static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a)
+{
+#ifdef TARGET_SPARC64
+ gen_helper_flushw(tcg_env);
+ return advance_pc(dc);
+#else
+ return false;
+#endif
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -3613,18 +3624,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
TCGv cpu_tmp0 __attribute__((unused));
-#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
- if (xop == 0x2b) { /* rdtbr / V9 flushw */
-#ifdef TARGET_SPARC64
- gen_helper_flushw(tcg_env);
-#else
- if (!supervisor(dc))
- goto priv_insn;
- gen_store_gpr(dc, rd, cpu_tbr);
-#endif
- break;
- }
-#endif
if (xop == 0x34) { /* FPU Operations */
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 23 +++++++++++------------ 2 files changed, 16 insertions(+), 12 deletions(-)