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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id a23-20020a50ff17000000b005342fa19070sm10081874edu.89.2023.10.12.05.19.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/8] hw/pci-host/designware: Hoist host controller in root function #0 Date: Thu, 12 Oct 2023 14:18:52 +0200 Message-ID: <20231012121857.31873-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There is always an unique root function for the host bridge controller. We create this function when the controller is realized, in designware_pcie_host_realize(). No need to call qdev_get_parent_bus() each time the root function want to resolve its host part. Hoist a pointer in its state. Set the pointer once when the function is realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gustavo Romero --- include/hw/pci-host/designware.h | 1 + hw/pci-host/designware.c | 15 +++++---------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index c484e377a8..9e2caa04e9 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -71,6 +71,7 @@ struct DesignwarePCIERoot { DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS]; DesignwarePCIEMSI msi; + DesignwarePCIEHost *host; }; struct DesignwarePCIEHost { diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index bacb2bdb2d..fb46493a05 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -57,13 +57,6 @@ #define DESIGNWARE_PCIE_IRQ_MSI 3 -static DesignwarePCIEHost * -designware_pcie_root_to_host(DesignwarePCIERoot *root) -{ - BusState *bus = qdev_get_parent_bus(DEVICE(root)); - return DESIGNWARE_PCIE_HOST(bus->parent); -} - static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, unsigned size) { @@ -85,7 +78,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = root->host; root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; @@ -300,7 +293,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, uint32_t val, int len) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = root->host; DesignwarePCIEViewport *viewport = designware_pcie_root_get_current_viewport(root); @@ -392,7 +385,8 @@ static char *designware_pcie_viewport_name(const char *direction, static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST( + qdev_get_parent_bus(DEVICE(dev))->parent); MemoryRegion *host_mem = get_system_memory(); MemoryRegion *address_space = &host->pci.memory; PCIBridge *br = PCI_BRIDGE(dev); @@ -406,6 +400,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) size_t i; br->bus_name = "dw-pcie"; + root->host = host; pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);