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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id n16-20020a05600c3b9000b0040684abb623sm19709208wms.24.2023.10.11.07.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 07:51:00 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v2 4/6] qemu/bitops.h: Add MAKE_32BIT_MASK macro Date: Wed, 11 Oct 2023 15:45:52 +0100 Message-ID: <20231011145032.81509-5-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231011145032.81509-1-rbradford@rivosinc.com> References: <20231011145032.81509-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add 32-bit version of mask generating macro and use it in the RISC-V PMU code. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- include/qemu/bitops.h | 3 +++ target/riscv/pmu.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index cb3526d1f4..9b25b2d5e4 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -25,6 +25,9 @@ #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define MAKE_32BIT_MASK(shift, length) \ + (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) + #define MAKE_64BIT_MASK(shift, length) \ (((~0ULL) >> (64 - (length))) << (shift)) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..360c76f63e 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -24,8 +24,6 @@ #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in