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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id e17-20020a2e8ed1000000b002c128e45245sm2985660ljl.23.2023.10.11.06.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 06:13:07 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 845EAA80; Wed, 11 Oct 2023 15:13:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1697029986; bh=F3oQPhMsKR40wMr+CadOwsJ3tRh25XuZhDfZ/k/ChV0=; h=From:To:Cc:Subject:Date:From; b=WOPOdOdfEHZhW0Z4cbVkziSjoXQE7ib64p6ypTfZNdVKe6Zayd2i3BV0pBvv1unsT 6WcRGZSFnCkzkKvIQD4zM3pOH6cngjslQmJ+FM8eFk/8JX2TATDjr1d5w3cAL/h6bB poz7EQqq9EsZQ9TYeJSWPYbgOuKTg4/aDKX0WWq4= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 52ED1A86; Wed, 11 Oct 2023 15:12:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1697029975; bh=F3oQPhMsKR40wMr+CadOwsJ3tRh25XuZhDfZ/k/ChV0=; h=From:To:Cc:Subject:Date:From; b=GgYe8rZHT6Rs0Uibtc3+YPIRjaAZdwhnTBktHDiV2ilj6QJsWQLjuNIl15XbYr+yy QskYj6Ktekv+ejeycEaEMGFVTzORyb0ikbVgbZJMHm+e6i1xpNUPtsfHMhuOwKPKMl v67ODL+uZxb7j43pJA7+xIC0FW0cuZDSxJR+7Xy0= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Michael Tokarev , Niklas Cassel Subject: [PATCH] hw/ide/ahci: trigger either error IRQ or regular IRQ, not both Date: Wed, 11 Oct 2023 15:12:20 +0200 Message-ID: <20231011131220.1992064-1-nks@flawful.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=nks.gnu@gmail.com; helo=mail-lj1-x22e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel According to AHCI 1.3.1, 5.3.8.1 RegFIS:Entry, if ERR_STAT is set, we jump to state ERR:FatalTaskfile, which will raise a TFES IRQ unconditionally, regardless if the I bit is set in the FIS or not. Thus, we should never raise a normal IRQ after having sent an error IRQ. NOTE: for QEMU platforms that use SeaBIOS, this patch depends on QEMU commit 784155cdcb02 ("seabios: update submodule to git snapshot"), and QEMU commit 14f5a7bae4cb ("seabios: update binaries to git snapshot"). Signed-off-by: Niklas Cassel Reviewed-by: Philippe Mathieu-Daudé --- hw/ide/ahci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index fcc5476e9e..7676e2d871 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -897,11 +897,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) pr->tfdata = (ad->port.ifs[0].error << 8) | ad->port.ifs[0].status; + /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ if (d2h_fis[2] & ERR_STAT) { ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); - } - - if (d2h_fis_i) { + } else if (d2h_fis_i) { ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); }