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Wed, 11 Oct 2023 00:03:55 -0700 (PDT) Received: from localhost ([157.82.206.10]) by smtp.gmail.com with UTF8SMTPSA id r29-20020a63205d000000b00565e2ad12e5sm10906685pgm.91.2023.10.11.00.03.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Oct 2023 00:03:55 -0700 (PDT) From: Akihiko Odaki To: Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Akihiko Odaki , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v9 03/23] target/riscv: Validate misa_mxl_max only once Date: Wed, 11 Oct 2023 16:02:49 +0900 Message-ID: <20231011070335.14398-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011070335.14398-1-akihiko.odaki@daynix.com> References: <20231011070335.14398-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::c2b; envelope-from=akihiko.odaki@daynix.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1306054d27..0c087df9f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1087,9 +1087,8 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) { - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); /* Validate that MISA_MXL is set properly. */ @@ -1487,8 +1486,6 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) return; } - riscv_cpu_validate_misa_mxl(cpu); - riscv_cpu_validate_priv_spec(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -2277,6 +2274,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *opaque) mcc->misa_mxl_max = data->misa_mxl_max; mcc->misa_ext_mask = data->misa_ext_mask; + + riscv_cpu_validate_misa_mxl(mcc); } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,