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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id ev5-20020a056402540500b0053b67aba57bsm4579372edb.17.2023.10.10.02.31.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 16/18] target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types Date: Tue, 10 Oct 2023 11:28:58 +0200 Message-ID: <20231010092901.99189-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/i386/cpu-qom.h" defines TYPE_X86_CPU depending on the i386/x86_64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new I386_CPU / X86_64_CPU types, both inheriting a common TYPE_X86_CPU base type. Keep the current "base" and "max" CPU types as 32 or 64-bit, depending on the binary built. Adapt the cpu-plug-test, since the 'base' architecture is now common to both 32/64-bit x86 targets. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- target/i386/cpu-qom.h | 16 +++++++++------- target/i386/cpu.h | 3 +++ target/i386/cpu.c | 20 ++++++++++++++++++-- tests/qtest/cpu-plug-test.c | 2 +- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 78207c0a7c..81f40bf91e 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU x86 CPU + * QEMU x86 CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -24,13 +24,15 @@ #include "qemu/notify.h" #include "qom/object.h" -#ifdef TARGET_X86_64 -#define TYPE_X86_CPU "x86_64-cpu" -#else -#define TYPE_X86_CPU "i386-cpu" -#endif +#define TYPE_X86_CPU "x86-cpu" +#define TYPE_I386_CPU "i386-cpu" +#define TYPE_X86_64_CPU "x86_64-cpu" -OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) +OBJECT_DECLARE_CPU_TYPE(I386CPU, X86CPUClass, I386_CPU) +OBJECT_DECLARE_CPU_TYPE(X86_64CPU, X86CPUClass, X86_64_CPU) + +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7c976971c7..5deb39a380 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -28,6 +28,9 @@ #include "qemu/cpu-float.h" #include "qemu/timer.h" +/* Abstract QOM X86 CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) + #define XEN_NR_VIRQS 24 /* The x86 has a strong memory model with some store-after-load re-ordering */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8f1fd5f304..1b1dae92c6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8033,12 +8033,28 @@ static const TypeInfo x86_cpu_types[] = { .class_size = sizeof(X86CPUClass), .class_init = x86_cpu_common_class_init, }, { - .name = X86_CPU_TYPE_NAME("base"), + .name = TYPE_I386_CPU, .parent = TYPE_X86_CPU, + .abstract = true, + }, { + .name = TYPE_X86_64_CPU, + .parent = TYPE_X86_CPU, + .abstract = true, + }, { + .name = X86_CPU_TYPE_NAME("base"), +#ifdef TARGET_X86_64 + .parent = TYPE_X86_64_CPU, +#else + .parent = TYPE_I386_CPU, +#endif .class_init = x86_cpu_base_class_init, }, { .name = X86_CPU_TYPE_NAME("max"), - .parent = TYPE_X86_CPU, +#ifdef TARGET_X86_64 + .parent = TYPE_X86_64_CPU, +#else + .parent = TYPE_I386_CPU, +#endif .instance_init = max_x86_cpu_initfn, .class_init = max_x86_cpu_class_init, } diff --git a/tests/qtest/cpu-plug-test.c b/tests/qtest/cpu-plug-test.c index 7f5dd5f85a..97316d131f 100644 --- a/tests/qtest/cpu-plug-test.c +++ b/tests/qtest/cpu-plug-test.c @@ -90,7 +90,7 @@ static void add_pc_test_case(const char *mname) data->machine = g_strdup(mname); data->cpu_model = "Haswell"; /* 1.3+ theoretically */ data->device_model = g_strdup_printf("%s-%s-cpu", data->cpu_model, - qtest_get_arch()); + qtest_get_base_arch()); data->sockets = 1; data->cores = 3; data->threads = 2;