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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id a14-20020a17090680ce00b0099cb1a2cab0sm8012503ejx.28.2023.10.10.00.50.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 00:50:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Laurent Vivier Subject: [PATCH 1/4] tests/libqtest: Introduce qtest_get_arch_bits() Date: Tue, 10 Oct 2023 09:49:49 +0200 Message-ID: <20231010074952.79165-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010074952.79165-1-philmd@linaro.org> References: <20231010074952.79165-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a method to return the architecture bits (currently 8/32/64). Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/libqtest.h | 8 ++++++++ tests/qtest/libqtest.c | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index e53e350e3a..1e1b42241d 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -654,6 +654,14 @@ bool qtest_big_endian(QTestState *s); */ const char *qtest_get_arch(void); +/** + * qtest_get_arch_bits: + * + * Returns: The architecture bits (a.k.a. word size) for the QEMU executable + * under test. + */ +unsigned qtest_get_arch_bits(void); + /** * qtest_has_accel: * @accel_name: Accelerator name to check for. diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index b1eba71ffe..a643a6309c 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -925,6 +925,27 @@ const char *qtest_get_arch(void) return end + 1; } +unsigned qtest_get_arch_bits(void) +{ + static const char *const arch64[] = { + "aarch64", "hppa", "x86_64", "loongarch64", "mips64", + "mips64el", "ppc64", "riscv64", "s390x", "sparc64", + }; + const char *arch = qtest_get_arch(); + + if (!strcmp(arch, "avr")) { + return 8; + } + + for (unsigned i = 0; i < ARRAY_SIZE(arch64); i++) { + if (!strcmp(arch, arch64[i])) { + return 64; + } + } + + return 32; +} + bool qtest_has_accel(const char *accel_name) { if (g_str_equal(accel_name, "tcg")) {