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(pd95eda61.dip0.t-ipconnect.de. [217.94.218.97]) by smtp.gmail.com with ESMTPSA id e27-20020a170906045b00b009b655c43710sm4241401eja.24.2023.10.07.05.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 05:39:24 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Chuck Zmudzinski , Marcel Apfelbaum , =?utf-8?q?Herv=C3=A9_Poussin?= =?utf-8?q?eau?= , Eduardo Habkost , Aurelien Jarno , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Richard Henderson , Bernhard Beschow Subject: [PATCH v8 28/29] hw/isa/piix: Implement multi-process QEMU support also for PIIX4 Date: Sat, 7 Oct 2023 14:38:36 +0200 Message-ID: <20231007123843.127151-29-shentey@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231007123843.127151-1-shentey@gmail.com> References: <20231007123843.127151-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org So far multi-process QEMU was only implemented for PIIX3. Move the support into the base class to achieve feature parity between both device models. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index cba2098ca2..04ebed5b52 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -374,6 +374,7 @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, } pci_bus_irqs(pci_bus, piix_set_pci_irq, d, PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq); } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -454,15 +455,7 @@ static const TypeInfo piix_pci_type_info = { static void piix3_realize(PCIDevice *dev, Error **errp) { - ERRP_GUARD(); - PCIBus *pci_bus = pci_get_bus(dev); - pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); - if (*errp) { - return; - } - - pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq); } static void piix3_init(Object *obj)