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([177.94.42.196]) by smtp.gmail.com with ESMTPSA id c12-20020a170902c1cc00b001c60a548331sm3796669plc.304.2023.10.06.06.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 06:21:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 06/10] target/riscv/tcg: commit profiles during realize() Date: Fri, 6 Oct 2023 10:21:30 -0300 Message-ID: <20231006132134.1135297-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231006132134.1135297-1-dbarboza@ventanamicro.com> References: <20231006132134.1135297-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To 'commit' a profile means enabling/disabling all its mandatory extensions after taking into account individual user choice w.r.t MISA and multi-letter extensions. We'll handle multi-letter extennsions now - MISA extensions needs additional steps that we'll take care later. riscv_cpu_manage_profiles() will scroll through all profiles available in QEMU and call riscv_cpu_commit_profile() for any profile that the user set, either to 'true' or 'false'. Setting a profile to 'true' means 'enable all mandatory extensions of this profile'. Setting it to 'false' means disabling all its mandatory extensions. Since we're doing it during realize() time we already have all user choices for individual extensions sorted out, and they'll take precedence. This will make us independent of left-to-right ordering in the QEMU command line, i.e. the following QEMU command lines: -cpu rv64,zicbom=false,rva22u64=true,Zifencei=false -cpu rv64,zicbom=false,Zifencei=false,rva22u64=true -cpu rv64,rva22u64=true,zicbom=false,Zifencei=false They mean the same thing: "enable all mandatory extensions of the rva22u64 profile while keeping zicbom and Zifencei disabled". Enabling extensions in the profile is also considered an user choice, so all extensions enabled will be added in the multi_ext_user_opts hash. Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a8ea869e6e..8fb77e9e35 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -264,6 +264,41 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } +static void riscv_cpu_commit_profile(RISCVCPU *cpu, RISCVCPUProfile *profile) +{ + int i; + + for (i = 0;; i++) { + int ext_offset = profile->ext_offsets[i]; + + if (ext_offset == RISCV_PROFILE_EXT_LIST_END) { + break; + } + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + continue; + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void riscv_cpu_manage_profiles(RISCVCPU *cpu) +{ + for (int i = 0; riscv_profiles[i] != NULL; i++) { + RISCVCPUProfile *profile = riscv_profiles[i]; + + if (!profile->user_set) { + continue; + } + + riscv_cpu_commit_profile(cpu, profile); + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -273,6 +308,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; Error *local_err = NULL; + riscv_cpu_manage_profiles(cpu); + /* Do some ISA extension error checking */ if (riscv_has_ext(env, RVG) && !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&