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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id n16-20020a2eb790000000b002b736576a10sm231887ljo.137.2023.10.05.02.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 02:53:46 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 75E38B825; Thu, 5 Oct 2023 11:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1696499625; bh=sckq77aRXO98P+R2IilWFCQxE9IIMhum/P/8l/R/AJU=; h=From:To:Cc:Subject:Date:From; b=ZZ6YUm0yVwkmoHwHVzATZGViL3uhr3wimrGKa+wNuxAP8gblIk6JsvoEgm83/SC8Q jjtMxvxwBvo3I59oVhIPdWd7Sd+YP5wc87lBdIE/jUStj+O45eIKwMQp8q+cJpBVRc 5swdhTQmJRU3eED1zzaC++yCZHxeEQJ5T0yz0Sz0= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 2E6733EEC; Thu, 5 Oct 2023 11:53:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1696499608; bh=sckq77aRXO98P+R2IilWFCQxE9IIMhum/P/8l/R/AJU=; h=From:To:Cc:Subject:Date:From; b=kZq0DIKMZoJcms2DyNBFLjBg/buQVGHwcXquyxyPzsBdktgY2OsgJgB6ir7RnQm8w RXQ1fPkcSegYZLjNG4XGp0inWgCYJyB05SNmZ3mdm7WdxUWH/hI4KKc9mHscs2OkiK At3/hz38ubkBWxEgShCMC1QLI5Jf2T58PXfWXPiU= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Marcin Juszkiewicz , Michael Tokarev , Niklas Cassel Subject: [PATCH] hw/ide/ahci: fix legacy software reset Date: Thu, 5 Oct 2023 11:53:21 +0200 Message-ID: <20231005095322.1133817-1-nks@flawful.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=nks.gnu@gmail.com; helo=mail-lj1-x232.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel Legacy software contains a standard mechanism for generating a reset to a Serial ATA device - setting the SRST (software reset) bit in the Device Control register. Serial ATA has a more robust mechanism called COMRESET, also referred to as port reset. A port reset is the preferred mechanism for error recovery and should be used in place of software reset. Commit e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") improved the handling of PxCI, such that PxCI gets cleared after handling a non-NCQ, or NCQ command (instead of incorrectly clearing PxCI after receiving an arbitrary FIS). However, simply clearing PxCI after a non-NCQ, or NCQ command, is not enough, we also need to clear PxCI when receiving a SRST in the Device Control register. This fixes an issue for FreeBSD where the device would fail to reset. The problem was not noticed in Linux, because Linux uses a COMRESET instead of a legacy software reset by default. Fixes: e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") Reported-by: Marcin Juszkiewicz Signed-off-by: Niklas Cassel Tested-by: Marcin Juszkiewicz --- hw/ide/ahci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index babdd7b458..3a8b97c325 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1254,10 +1254,26 @@ static void handle_reg_h2d_fis(AHCIState *s, int port, case STATE_RUN: if (cmd_fis[15] & ATA_SRST) { s->dev[port].port_state = STATE_RESET; + /* + * When setting SRST in the first H2D FIS in the reset sequence, + * the device does not send a D2H FIS. Host software thus has to + * set the "Clear Busy upon R_OK" bit such that PxCI (and BUSY) + * gets cleared. See AHCI 1.3.1, section 10.4.1 Software Reset. + */ + if (opts & AHCI_CMD_CLR_BUSY) { + ahci_clear_cmd_issue(ad, slot); + } } break; case STATE_RESET: if (!(cmd_fis[15] & ATA_SRST)) { + /* + * When clearing SRST in the second H2D FIS in the reset + * sequence, the device will send a D2H FIS. See SATA 3.5a Gold, + * section 11.4 Software reset protocol. + */ + ahci_write_fis_d2h(ad, false); + ahci_clear_cmd_issue(ad, slot); ahci_reset_port(s, port); } break;