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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c234900b00405c7591b09sm701014wmq.35.2023.10.03.01.28.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:28:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/5] hw/intc/apic: Pass CPU using QOM link property Date: Tue, 3 Oct 2023 10:27:28 +0200 Message-ID: <20231003082728.83496-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org QOM objects shouldn't access each other internals fields except using the QOM API. Declare the 'cpu' and 'base-addr' properties, set them using object_property_set_link() and qdev_prop_set_uint32() respectively. Since the _set_link() call can't fail, use &error_abort in case there is a programming error. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/apic_common.c | 2 ++ target/i386/cpu-sysemu.c | 9 ++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 8a79eacdb0..be7cf3b332 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -398,6 +398,8 @@ static Property apic_properties_common[] = { true), DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, false), + DEFINE_PROP_LINK("cpu", APICCommonState, cpu, TYPE_X86_CPU, X86CPU *), + DEFINE_PROP_UINT32("base-addr", APICCommonState, apicbase, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 373dc6b1c7..b084706531 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -265,7 +265,6 @@ APICCommonClass *apic_get_class(void) void x86_cpu_apic_new(X86CPU *cpu) { - APICCommonState *apic; APICCommonClass *apic_class = apic_get_class(); cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); @@ -273,11 +272,11 @@ void x86_cpu_apic_new(X86CPU *cpu) OBJECT(cpu->apic_state)); object_unref(OBJECT(cpu->apic_state)); + object_property_set_link(OBJECT(cpu->apic_state), "cpu", + OBJECT(cpu), &error_abort); qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); - /* TODO: convert to link<> */ - apic = APIC_COMMON(cpu->apic_state); - apic->cpu = cpu; - apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; + qdev_prop_set_uint32(cpu->apic_state, "base-addr", + APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE); } void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)