@@ -84,6 +84,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
+ ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_ihpm),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
@@ -1267,10 +1268,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
/*
- * Always default true - we'll disable it during
+ * Always default true - we'll disable them during
* realize() if needed.
*/
MULTI_EXT_CFG_BOOL("zicntr", ext_icntr, true),
+ MULTI_EXT_CFG_BOOL("zihpm", ext_ihpm, true),
MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
@@ -66,6 +66,7 @@ struct RISCVCPUConfig {
bool ext_icsr;
bool ext_icbom;
bool ext_icboz;
+ bool ext_ihpm;
bool ext_zicond;
bool ext_zihintntl;
bool ext_zihintpause;
@@ -546,6 +546,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_icntr = false;
}
+ if (cpu->cfg.ext_ihpm && (!cpu->cfg.ext_icsr || cpu->cfg.pmu_num == 0)) {
+ cpu->cfg.ext_ihpm = false;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
zihpm is the Hardware Performance Counters extension described in chapter 12 of the unprivileged spec. It describes support for 29 unprivileged performance counters, hpmcounter3-hpmcounter21. As with zicntr, QEMU already implements zihpm before it was even an extension. zihpm is also part of the RVA22 profile, so add it to QEMU to complement the future future profile implementation. Default it to 'true' since it was always present in the code. Change the realize() time validation to disable it in case 'icsr' isn't present and if there's no hardware counters (cpu->cfg.pmu_num is zero). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-)