From patchwork Mon Sep 25 05:03:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Bowler X-Patchwork-Id: 1839056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RvNGY1xMxz1yqR for ; Mon, 25 Sep 2023 22:58:29 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8p-0008Ko-EI; Mon, 25 Sep 2023 08:56:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0001eQ-Qu for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjr-0004mt-6S for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:33 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 9E93720777; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 77E232076F; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 4/8] target/sparc: Fix VIS fmuld8sux16 instruction. Date: Mon, 25 Sep 2023 01:03:53 -0400 Message-ID: <20230925050545.30912-5-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On a real UltraSparc II, the fmuld8sux16 instruction takes two single- precision input operands and returns a double-precision result. However, the emulation is taking two double-precision input operands, which are unlikely to contain the correct values. Even if they did, the emulator is rounding the output, which the real processor does not do. And the real processor shifts both outputs left by 8, which the emulator does not do. So the results are wrong except in trivial cases. Signed-off-by: Nick Bowler Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 2 +- target/sparc/vis_helper.c | 19 ++++++++----------- 3 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 25d6178ca5..adc1ea6653 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -131,7 +131,7 @@ DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dddee9f974..1017d3bca7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4791,7 +4791,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x038: /* VIS I fmuld8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); + gen_ne_fop_DFF(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); break; case 0x039: /* VIS I fmuld8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 386cfd0706..de5ddad39a 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -220,24 +220,21 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fmuld8sux16(uint64_t src1, uint64_t src2) +uint64_t helper_fmuld8sux16(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; uint32_t tmp; - s.ll = src1; - d.ll = src2; + s1.l = src1; + s2.l = src2; #define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_L64(r) = tmp; + tmp = (int32_t)s2.VIS_SW32(r) * ((int32_t)s1.VIS_SW32(r) >> 8); \ + d.VIS_L64(r) = tmp << 8; - /* Reverse calculation order to handle overlap */ - PMUL(1); PMUL(0); + PMUL(1); #undef PMUL return d.ll;