diff mbox series

[13/14] hw/arm: Connect to chardev backend for NPCM8XX

Message ID 20230919175725.3413108-14-nabihestefan@google.com
State New
Headers show
Series Implementation of NPI Mailbox and GMAC Networking Module | expand

Commit Message

Nabih Estefan Sept. 19, 2023, 5:57 p.m. UTC 
From: Hao Wu <wuhaotsh@google.com>

As NPCM8XX SoCs have 2 mailboxes, we can't use -global to connect
the mailboxes to their specific chardevs. So we add the search
for chardev code here, similar to what we did for the GMAC devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
---
 hw/arm/npcm8xx.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index a9eb2b894c..8859cb274d 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -16,6 +16,7 @@ 
 
 #include "qemu/osdep.h"
 
+#include "chardev/char.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/npcm8xx.h"
 #include "hw/char/serial.h"
@@ -25,7 +26,9 @@ 
 #include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
+#include "qemu/error-report.h"
 #include "qemu/units.h"
+#include "qom/object.h"
 #include "sysemu/sysemu.h"
 
 #define ARM_PHYS_TIMER_PPI  30
@@ -762,6 +765,14 @@  static void npcm8xx_realize(DeviceState *dev, Error **errp)
 
     /* PCI Mailbox. Cannot fail */
     for (i = 0; i < ARRAY_SIZE(s->pci_mbox); i++) {
+        g_autofree char *char_name = g_strdup_printf("pci%d", i);
+        Chardev *chardev = qemu_chr_find(char_name);
+
+        if (chardev) {
+            qdev_prop_set_chr(DEVICE(&s->pci_mbox[i]), "chardev", chardev);
+        } else {
+            warn_report("PCI Mailbox %d does not have a chardev backend.", i);
+        }
         sysbus_realize(SYS_BUS_DEVICE(&s->pci_mbox[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox[i]), 0,
                                        npcm8xx_pci_mbox_addr[i]);