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Tue, 19 Sep 2023 10:57:56 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:20 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-10-nabihestefan@google.com> Subject: [PATCH 09/14] include/hw/net: Implemented Classes and Masks for GMAC Descriptors From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3JOEJZQwKCj0mZahgdrsdeZmfnnfkd.bnlpdlt-cdudkmnmfmt.nqf@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Nabih Estefan Diaz - Implemeted classes for GMAC Receive and Transmit Descriptors - Implemented Masks for said descriptors Signed-off-by: Nabih Estefan Diaz --- include/hw/net/npcm_gmac.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/hw/net/npcm_gmac.h b/include/hw/net/npcm_gmac.h index 03529db1d6..067928fe0b 100644 --- a/include/hw/net/npcm_gmac.h +++ b/include/hw/net/npcm_gmac.h @@ -38,12 +38,19 @@ struct NPCMGMACRxDesc { /* RDES2 and RDES3 are buffer address pointers */ /* Owner: 0 = software, 1 = gmac */ #define RX_DESC_RDES0_OWNER_MASK BIT(31) +<<<<<<< HEAD /* Owner*/ #define RX_DESC_RDES0_OWNER_SHIFT 31 /* Destination Address Filter Fail */ #define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) /* Frame length*/ #define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 29) +======= +/* Destination Address Filter Fail */ +#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) +/* Frame length*/ +#define RX_DESC_RDES0_FRAME_LEN_MASK extract32(rdes0, 16, 29) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC Descriptors) /* Error Summary */ #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15) /* Descriptor Error */ @@ -84,11 +91,17 @@ struct NPCMGMACRxDesc { /* Second Address Chained */ #define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24) /* Receive Buffer 2 Size */ +<<<<<<< HEAD #define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11 #define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \ RX_DESC_RDES1_BFFR2_SZ_SHIFT, 10 + RX_DESC_RDES1_BFFR2_SZ_SHIFT) /* Receive Buffer 1 Size */ #define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) +======= +#define RX_DESC_RDES1_BFFR2_SZ_MASK extract32(rdes1, 11, 21) +/* Receive Buffer 1 Size */ +#define RX_DESC_RDES1_BFFR1_SZ_MASK extract32(rdes1, 0, 10) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC Descriptors) struct NPCMGMACTxDesc { @@ -125,7 +138,11 @@ struct NPCMGMACTxDesc { /* VLAN Frame */ #define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7) /* Collision Count */ +<<<<<<< HEAD #define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 6) +======= +#define TX_DESC_TDES0_COLL_CNT_MASK extract32(tdes0, 3, 6) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC Descriptors) /* Excessive Deferral */ #define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2) /* Underflow Error */ @@ -140,7 +157,11 @@ struct NPCMGMACTxDesc { /* Last Segment */ #define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29) /* Checksum Insertion Control */ +<<<<<<< HEAD #define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 28) +======= +#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK extract32(tdes1, 27, 28) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC Descriptors) /* Disable Cyclic Redundancy Check */ #define TX_DESC_TDES1_DIS_CDC_MASK BIT(26) /* Transmit End of Ring */ @@ -148,9 +169,15 @@ struct NPCMGMACTxDesc { /* Secondary Address Chained */ #define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24) /* Transmit Buffer 2 Size */ +<<<<<<< HEAD #define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 21) /* Transmit Buffer 1 Size */ #define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) +======= +#define TX_DESC_TDES1_BFFR2_SZ_MASK extract32(tdes1, 11, 21) +/* Transmit Buffer 1 Size */ +#define TX_DESC_TDES1_BFFR1_SZ_MASK extract32(tdes1, 0, 10) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC Descriptors) typedef struct NPCMGMACState { SysBusDevice parent;