From patchwork Thu Sep 14 07:21:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 1834082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=hkEUbjcp; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RmT7d3vmHz1ypW for ; Thu, 14 Sep 2023 17:13:33 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qggXB-00055l-Vi; Thu, 14 Sep 2023 03:13:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qggX5-0004wR-Vt for qemu-devel@nongnu.org; Thu, 14 Sep 2023 03:13:00 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qggX3-0006IN-G3 for qemu-devel@nongnu.org; Thu, 14 Sep 2023 03:12:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694675577; x=1726211577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MhOfVJY580KfIp4Fybth+wo1ybI2RWPtBwiUTz324Nk=; b=hkEUbjcpC6a47ZOGHKYoRtnvSyKOWGeZkkvhtUxpyItbHdvX2peFnIw4 vKMCMc9qo06oDD/shtkJgBpCCjchBslAHqUq0fYNRpsPcojaufuVR+sIP me+6qfsSPK5gRwBBQeAllnqaIskEZGqLT+DMXQeLgzfd3nQPc6g0NodzU gHbae4tbPA6viRw0AFj0PgYv7vbt2d3HWM/g4bjfxLpPN6rD5iJTPnBjL DYeFfgm3FfmJkcIZWragURbmSDjhGtMb1FXhDyrERFVBhlhlQ2zT9cMMd 5Ivbrr5fQYTijwkk/bBi+kk5hSqP9bXJeQmWLsHyNQsbOpytkwafx1W9M w==; X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="359136796" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="359136796" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2023 00:12:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="779526871" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="779526871" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga001.jf.intel.com with ESMTP; 14 Sep 2023 00:12:36 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Yongwei Ma Subject: [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H Date: Thu, 14 Sep 2023 15:21:59 +0800 Message-Id: <20230914072159.1177582-22-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230914072159.1177582-1-zhao1.liu@linux.intel.com> References: <20230914072159.1177582-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.151; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache topology will be overrode by the new topology setting. Here we expose to user "cluster" instead of "module", to be consistent with "cluster-id" naming. Since CPUID.04H is used by intel CPUs, this property is available on intel CPUs as for now. When necessary, it can be extended to CPUID.8000001DH for AMD CPUs. (Tested the cache topology in CPUID[0x04] leaf with "x-l2-cache-topo=[ core|cluster]", and tested the live migration between the QEMUs w/ & w/o this patch series.) Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- Changes since v3: * Add description about test for live migration compatibility. (Babu) Changes since v1: * Rename MODULE branch to CPU_TOPO_LEVEL_MODULE to match the previous renaming changes. --- target/i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- target/i386/cpu.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3bed823dc3b7..b1282c8bd3b7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,6 +243,9 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,7 +254,7 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo *topo_info, break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for SMT, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -7576,6 +7579,34 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->cache_info_amd.l3_cache = &legacy_l3_cache; } + if (cpu->l2_cache_topo_level) { + /* + * FIXME: Currently only supports changing CPUID[4] (for intel), and + * will support changing CPUID[0x8000001D] when necessary. + */ + if (!IS_INTEL_CPU(env)) { + error_setg(errp, "only intel cpus supports x-l2-cache-topo"); + return; + } + + if (!strcmp(cpu->l2_cache_topo_level, "core")) { + env->cache_info_cpuid4.l2_cache->share_level = CPU_TOPO_LEVEL_CORE; + } else if (!strcmp(cpu->l2_cache_topo_level, "cluster")) { + /* + * We expose to users "cluster" instead of "module", to be + * consistent with "cluster-id" naming. + */ + env->cache_info_cpuid4.l2_cache->share_level = + CPU_TOPO_LEVEL_MODULE; + } else { + error_setg(errp, + "x-l2-cache-topo doesn't support '%s', " + "and it only supports 'core' or 'cluster'", + cpu->l2_cache_topo_level); + return; + } + } + #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); @@ -8079,6 +8110,7 @@ static Property x86_cpu_properties[] = { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level), DEFINE_PROP_END_OF_LIST() }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a13132007415..05ffc4c1cc6e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2073,6 +2073,8 @@ struct ArchCPU { int32_t hv_max_vps; bool xen_vapic; + + char *l2_cache_topo_level; };