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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id x24-20020a170902b41800b001bbdf32f011sm304336plr.269.2023.09.13.19.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 19:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anjo@rev.ng, ale@rev.ng, philmd@linaro.org Subject: [PATCH v2 09/24] accel/tcg: Remove CPUState.icount_decr_ptr Date: Wed, 13 Sep 2023 19:44:20 -0700 Message-Id: <20230914024435.1381329-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230914024435.1381329-1-richard.henderson@linaro.org> References: <20230914024435.1381329-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We can now access icount_decr directly. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/hw/core/cpu.h | 2 -- hw/core/cpu-common.c | 4 ++-- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c3c78ed8ab..3b01e4ee25 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -434,7 +434,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr = &cpu->env; - cpu->parent_obj.icount_decr_ptr = &cpu->parent_obj.neg.icount_decr; } /* Validate correct placement of CPUArchState. */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1f289136ec..44955af3bc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -440,7 +440,6 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets which * only have a single AddressSpace * @env_ptr: Pointer to subclass-specific CPUArchState field. - * @icount_decr_ptr: Pointer to IcountDecr field within subclass. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -512,7 +511,6 @@ struct CPUState { MemoryRegion *memory; CPUArchState *env_ptr; - IcountDecr *icount_decr_ptr; CPUJumpCache *tb_jmp_cache; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ced66c2b34..08d5bbc873 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -86,7 +86,7 @@ void cpu_exit(CPUState *cpu) qatomic_set(&cpu->exit_request, 1); /* Ensure cpu_exec will see the exit request after TCG has exited. */ smp_wmb(); - qatomic_set(&cpu->icount_decr_ptr->u16.high, -1); + qatomic_set(&cpu->neg.icount_decr.u16.high, -1); } static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) @@ -130,7 +130,7 @@ static void cpu_common_reset_hold(Object *obj) cpu->halted = cpu->start_powered_off; cpu->mem_io_pc = 0; cpu->icount_extra = 0; - qatomic_set(&cpu->icount_decr_ptr->u32, 0); + qatomic_set(&cpu->neg.icount_decr.u32, 0); cpu->can_do_io = 1; cpu->exception_index = -1; cpu->crash_occurred = false;