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Tue, 12 Sep 2023 17:58:34 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Richard Henderson , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz , qemu-devel@nongnu.org Subject: [RFC PATCH 3/3] target/ppc: Optimise after CR register tl conversion Date: Wed, 13 Sep 2023 10:58:14 +1000 Message-Id: <20230913005814.413113-4-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230913005814.413113-1-npiggin@gmail.com> References: <20230913005814.413113-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org After changing CR registers from i32 to tl, a number of places that that previously did type conversion are now redundant moves between variables that can be removed. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 97 +++++++++------------- target/ppc/translate/fixedpoint-impl.c.inc | 3 +- target/ppc/translate/fp-impl.c.inc | 17 +--- 4 files changed, 46 insertions(+), 73 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3472697b30..8fdc3f3546 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1471,21 +1471,18 @@ static opc_handler_t invalid_handler = { static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) { - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t = tcg_temp_new(); + TCGv tmp = tcg_temp_new(); + TCGv cr = cpu_crf[crf]; - tcg_gen_movi_tl(t0, CRF_EQ); - tcg_gen_movi_tl(t1, CRF_LT); + tcg_gen_movi_tl(cr, CRF_EQ); + tcg_gen_movi_tl(tmp, CRF_LT); tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), - t0, arg0, arg1, t1, t0); - tcg_gen_movi_tl(t1, CRF_GT); + cr, arg0, arg1, tmp, cr); + tcg_gen_movi_tl(tmp, CRF_GT); tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), - t0, arg0, arg1, t1, t0); + cr, arg0, arg1, tmp, cr); - tcg_gen_mov_tl(t, t0); - tcg_gen_mov_tl(cpu_crf[crf], cpu_so); - tcg_gen_or_tl(cpu_crf[crf], cpu_crf[crf], t); + tcg_gen_or_tl(cr, cr, cpu_so); } static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) @@ -1531,19 +1528,16 @@ static void gen_cmprb(DisasContext *ctx) TCGv src2 = tcg_temp_new(); TCGv src2lo = tcg_temp_new(); TCGv src2hi = tcg_temp_new(); - TCGv crf = cpu_crf[crfD(ctx->opcode)]; - - tcg_gen_mov_tl(src1, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_mov_tl(src2, cpu_gpr[rB(ctx->opcode)]); + TCGv cr = cpu_crf[crfD(ctx->opcode)]; - tcg_gen_andi_tl(src1, src1, 0xFF); - tcg_gen_ext8u_tl(src2lo, src2); - tcg_gen_shri_tl(src2, src2, 8); + tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); + tcg_gen_ext8u_tl(src2lo, cpu_gpr[rB(ctx->opcode)]); + tcg_gen_shri_tl(src2, cpu_gpr[rB(ctx->opcode)], 8); tcg_gen_ext8u_tl(src2hi, src2); tcg_gen_setcond_tl(TCG_COND_LEU, src2lo, src2lo, src1); tcg_gen_setcond_tl(TCG_COND_LEU, src2hi, src1, src2hi); - tcg_gen_and_tl(crf, src2lo, src2hi); + tcg_gen_and_tl(cr, src2lo, src2hi); if (ctx->opcode & 0x00200000) { tcg_gen_shri_tl(src2, src2, 8); @@ -1553,9 +1547,9 @@ static void gen_cmprb(DisasContext *ctx) tcg_gen_setcond_tl(TCG_COND_LEU, src2lo, src2lo, src1); tcg_gen_setcond_tl(TCG_COND_LEU, src2hi, src1, src2hi); tcg_gen_and_tl(src2lo, src2lo, src2hi); - tcg_gen_or_tl(crf, crf, src2lo); + tcg_gen_or_tl(cr, cr, src2lo); } - tcg_gen_shli_tl(crf, crf, CRF_GT_BIT); + tcg_gen_shli_tl(cr, cr, CRF_GT_BIT); } #if defined(TARGET_PPC64) @@ -1572,11 +1566,11 @@ static void gen_isel(DisasContext *ctx) { uint32_t bi = rC(ctx->opcode); uint32_t mask = 0x08 >> (bi & 0x03); + TCGv cr = cpu_crf[bi >> 2]; TCGv t0 = tcg_temp_new(); TCGv zr; - tcg_gen_mov_tl(t0, cpu_crf[bi >> 2]); - tcg_gen_andi_tl(t0, t0, mask); + tcg_gen_andi_tl(t0, cr, mask); zr = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, @@ -3806,13 +3800,12 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) { TCGLabel *lfail; TCGv EA; - TCGv cr0; + TCGv cr0 = cpu_crf[0]; TCGv t0; int rs = rS(ctx->opcode); lfail = gen_new_label(); EA = tcg_temp_new(); - cr0 = tcg_temp_new(); t0 = tcg_temp_new(); tcg_gen_mov_tl(cr0, cpu_so); @@ -3829,7 +3822,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) tcg_gen_or_tl(cr0, cr0, t0); gen_set_label(lfail); - tcg_gen_mov_tl(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } @@ -3885,7 +3877,7 @@ static void gen_stqcx_(DisasContext *ctx) { TCGLabel *lfail; TCGv EA, t0, t1; - TCGv cr0; + TCGv cr0 = cpu_crf[0]; TCGv_i128 cmp, val; int rs = rS(ctx->opcode); @@ -3896,7 +3888,6 @@ static void gen_stqcx_(DisasContext *ctx) lfail = gen_new_label(); EA = tcg_temp_new(); - cr0 = tcg_temp_new(); tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); @@ -3928,7 +3919,6 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_or_tl(cr0, cr0, t0); gen_set_label(lfail); - tcg_gen_mov_tl(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */ @@ -4680,34 +4670,30 @@ static void gen_mcrxrx(DisasContext *ctx) /* mfcr mfocrf */ static void gen_mfcr(DisasContext *ctx) { + TCGv dst = cpu_gpr[rD(ctx->opcode)]; uint32_t crm, crn; if (likely(ctx->opcode & 0x00100000)) { crm = CRM(ctx->opcode); if (likely(crm && ((crm & (crm - 1)) == 0))) { crn = ctz32(crm); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], crn * 4); + tcg_gen_shli_tl(dst, cpu_crf[7 - crn], crn * 4); } } else { - TCGv t0 = tcg_temp_new(); - tcg_gen_mov_tl(t0, cpu_crf[0]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[1]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[2]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[3]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[4]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[5]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[6]); - tcg_gen_shli_tl(t0, t0, 4); - tcg_gen_or_tl(t0, t0, cpu_crf[7]); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_gen_shli_tl(dst, cpu_crf[0], 4); + tcg_gen_or_tl(dst, dst, cpu_crf[1]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[2]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[3]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[4]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[5]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[6]); + tcg_gen_shli_tl(dst, dst, 4); + tcg_gen_or_tl(dst, dst, cpu_crf[7]); } } @@ -4794,23 +4780,22 @@ static void gen_mftb(DisasContext *ctx) /* mtcrf mtocrf*/ static void gen_mtcrf(DisasContext *ctx) { + TCGv src = cpu_gpr[rS(ctx->opcode)]; uint32_t crm, crn; crm = CRM(ctx->opcode); if (likely((ctx->opcode & 0x00100000))) { if (crm && ((crm & (crm - 1)) == 0)) { - TCGv temp = tcg_temp_new(); + TCGv crf; crn = ctz32(crm); - tcg_gen_mov_tl(temp, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_shri_tl(temp, temp, crn * 4); - tcg_gen_andi_tl(cpu_crf[7 - crn], temp, 0xf); + crf = cpu_crf[7 - crn]; + tcg_gen_shri_tl(crf, src, crn * 4); + tcg_gen_andi_tl(crf, crf, 0xf); } } else { - TCGv temp = tcg_temp_new(); - tcg_gen_mov_tl(temp, cpu_gpr[rS(ctx->opcode)]); for (crn = 0 ; crn < 8 ; crn++) { if (crm & (1 << crn)) { - tcg_gen_shri_tl(cpu_crf[7 - crn], temp, crn * 4); + tcg_gen_shri_tl(cpu_crf[7 - crn], src, crn * 4); tcg_gen_andi_tl(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); } } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 1ad4049df6..17cd3febb9 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -344,8 +344,7 @@ static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) TCGv temp = tcg_temp_new(); TCGv zero = tcg_constant_tl(0); - tcg_gen_mov_tl(temp, cpu_crf[a->bi >> 2]); - tcg_gen_andi_tl(temp, temp, mask); + tcg_gen_andi_tl(temp, cpu_crf[a->bi >> 2], mask); if (neg) { tcg_gen_negsetcond_tl(cond, cpu_gpr[a->rt], temp, zero); } else { diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index 9f71c039ce..1d986c26eb 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -15,19 +15,10 @@ static inline void gen_compute_fprf_float64(TCGv_i64 arg) gen_helper_float_check_status(cpu_env); } -#if defined(TARGET_PPC64) -static void gen_set_cr1_from_fpscr(DisasContext *ctx) -{ - TCGv tmp = tcg_temp_new(); - tcg_gen_mov_tl(tmp, cpu_fpscr); - tcg_gen_shri_tl(cpu_crf[1], tmp, FPSCR_OX); -} -#else static void gen_set_cr1_from_fpscr(DisasContext *ctx) { tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, FPSCR_OX); } -#endif /*** Floating-Point arithmetic ***/ #define _GEN_FLOAT_ACB(name, op1, op2, set_fprf, type) \ @@ -518,7 +509,7 @@ static void gen_fmrgow(DisasContext *ctx) /* mcrfs */ static void gen_mcrfs(DisasContext *ctx) { - TCGv tmp = tcg_temp_new(); + TCGv cr = cpu_crf[crfD(ctx->opcode)]; TCGv_i32 tmask; TCGv_i64 tnew_fpscr = tcg_temp_new_i64(); int bfa; @@ -532,10 +523,8 @@ static void gen_mcrfs(DisasContext *ctx) bfa = crfS(ctx->opcode); nibble = 7 - bfa; shift = 4 * nibble; - tcg_gen_shri_tl(tmp, cpu_fpscr, shift); - tcg_gen_mov_tl(cpu_crf[crfD(ctx->opcode)], tmp); - tcg_gen_andi_tl(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], - 0xf); + tcg_gen_shri_tl(cr, cpu_fpscr, shift); + tcg_gen_andi_tl(cr, cr, 0xf); tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); /* Only the exception bits (including FX) should be cleared if read */ tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,