diff mbox series

[Stable-8.0.5,12/43] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

Message ID 20230909130020.352951-12-mjt@tls.msk.ru
State New
Headers show
Series Patch Round-up for stable 8.0.5, freeze on 2023-09-19 | expand

Commit Message

Michael Tokarev Sept. 9, 2023, 12:59 p.m. UTC 
From: Nathan Egge <negge@xiph.org>

Set V bit for hwcap if misa is set.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
Signed-off-by: Nathan Egge <negge@xiph.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230803131424.40744-1-negge@xiph.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit 4333f0924c2f2ca8efaebaed8c24f55f77d8b013)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff mbox series

Patch

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 88ef26dc03..a3e78a7e18 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1679,7 +1679,8 @@  static uint32_t get_elf_hwcap(void)
 #define MISA_BIT(EXT) (1 << (EXT - 'A'))
     RISCVCPU *cpu = RISCV_CPU(thread_cpu);
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V');
 
     return cpu->env.misa_ext & mask;
 #undef MISA_BIT