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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:53 -0700 (PDT) From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, zhiwei_liu@linux.alibaba.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v1 5/8] target/riscv: Add pointer masking tb flags Date: Fri, 8 Sep 2023 18:26:37 +0000 Message-Id: <20230908182640.1102270-6-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230908182640.1102270-1-baturo.alexey@gmail.com> References: <20230908182640.1102270-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 19 +++++++++++++------ target/riscv/cpu_helper.c | 4 ++++ target/riscv/translate.c | 10 ++++++++++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 25fe60476b..17d0088cb4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,6 +356,10 @@ struct CPUArchState { target_ulong senvcfg; uint64_t henvcfg; #endif + /* current number of masked top bits by pointer masking */ + target_ulong pm_n_bits; + /* if pointer masking should do sign extension */ + bool pm_signext; /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -492,14 +496,17 @@ FIELD(TB_FLAGS, VILL, 14, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) -FIELD(TB_FLAGS, VTA, 18, 1) -FIELD(TB_FLAGS, VMA, 19, 1) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 20, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) -FIELD(TB_FLAGS, PRIV, 22, 2) -FIELD(TB_FLAGS, AXL, 24, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) +FIELD(TB_FLAGS, PRIV, 24, 2) +FIELD(TB_FLAGS, AXL, 25, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57859314e3..b3871b0a28 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,6 +136,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + if (env->pm_n_bits != 0) { + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, 1); + } + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, env->pm_signext); *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce47904590..3434ba58b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,6 +42,8 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* number of top masked address bits by pointer masking extension */ +static TCGv pm_n_bits; /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -103,6 +105,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* pointer masking extension */ + bool pm_enabled; + bool pm_signext; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1175,6 +1180,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_signext = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; @@ -1306,4 +1313,7 @@ void riscv_translate_init(void) "load_res"); load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), "load_val"); + /* Assign var with number of pointer masking masked bits to tcg global */ + pm_n_bits = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pm_n_bits), + "pmbits"); }