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Thu, 07 Sep 2023 06:00:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaR8KoqTaBs4QMMVM27YTMz2ib1u+oBtbcxG28ys0ImMJXzgMHNt8rtKly2KrNBXWmBqKA+w== X-Received: by 2002:adf:db0f:0:b0:317:f702:70d8 with SMTP id s15-20020adfdb0f000000b00317f70270d8mr4493047wri.67.1694091612936; Thu, 07 Sep 2023 06:00:12 -0700 (PDT) Received: from [192.168.1.174] ([151.48.237.81]) by smtp.gmail.com with ESMTPSA id cc11-20020a5d5c0b000000b0031f34a395e7sm17004439wrb.45.2023.09.07.06.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 06:00:12 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 02/51] target/i386: raise FERR interrupt with iothread locked Date: Thu, 7 Sep 2023 14:59:11 +0200 Message-ID: <20230907130004.500601-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230907130004.500601-1-pbonzini@redhat.com> References: <20230907130004.500601-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Otherwise tcg_handle_interrupt() triggers an assertion failure: #5 0x0000555555c97369 in tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:83 #6 tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:81 #7 0x0000555555b4d58b in pic_irq_request (opaque=, irq=, level=1) at ../hw/i386/x86.c:555 #8 0x0000555555b4f218 in gsi_handler (opaque=0x5555579423d0, n=13, level=1) at ../hw/i386/x86.c:611 #9 0x00007fffa42bde14 in code_gen_buffer () #10 0x0000555555c724bb in cpu_tb_exec (cpu=cpu@entry=0x555557434cb0, itb=, tb_exit=tb_exit@entry=0x7fffe9bfd658) at ../accel/tcg/cpu-exec.c:457 Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1808 Reported-by: NyanCatTW1 Co-developed-by: Richard Henderson ' Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- target/i386/tcg/sysemu/fpu_helper.c | 6 ++++++ target/i386/tcg/translate.c | 8 +++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/sysemu/fpu_helper.c b/target/i386/tcg/sysemu/fpu_helper.c index 1c3610da3b9..93506cdd94e 100644 --- a/target/i386/tcg/sysemu/fpu_helper.c +++ b/target/i386/tcg/sysemu/fpu_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "hw/irq.h" @@ -31,7 +32,9 @@ void x86_register_ferr_irq(qemu_irq irq) void fpu_check_raise_ferr_irq(CPUX86State *env) { if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) { + qemu_mutex_lock_iothread(); qemu_irq_raise(ferr_irq); + qemu_mutex_unlock_iothread(); return; } } @@ -45,6 +48,9 @@ void cpu_clear_ignne(void) void cpu_set_ignne(void) { CPUX86State *env = &X86_CPU(first_cpu)->env; + + assert(qemu_mutex_iothread_locked()); + env->hflags2 |= HF2_IGNNE_MASK; /* * We get here in response to a write to port F0h. The chipset should diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 90c7b32f362..e0a622941cb 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -4619,7 +4619,11 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x0a: /* grp d9/2 */ switch (rm) { case 0: /* fnop */ - /* check exceptions (FreeBSD FPU probe) */ + /* + * check exceptions (FreeBSD FPU probe) + * needs to be treated as I/O because of ferr_irq + */ + translator_io_start(&s->base); gen_helper_fwait(cpu_env); update_fip = false; break; @@ -5548,6 +5552,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) (HF_MP_MASK | HF_TS_MASK)) { gen_exception(s, EXCP07_PREX); } else { + /* needs to be treated as I/O because of ferr_irq */ + translator_io_start(&s->base); gen_helper_fwait(cpu_env); } break;