@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "hw/irq.h"
@@ -31,7 +32,9 @@ void x86_register_ferr_irq(qemu_irq irq)
void fpu_check_raise_ferr_irq(CPUX86State *env)
{
if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
+ qemu_mutex_lock_iothread();
qemu_irq_raise(ferr_irq);
+ qemu_mutex_unlock_iothread();
return;
}
}
@@ -45,6 +48,9 @@ void cpu_clear_ignne(void)
void cpu_set_ignne(void)
{
CPUX86State *env = &X86_CPU(first_cpu)->env;
+
+ assert(qemu_mutex_iothread_locked());
+
env->hflags2 |= HF2_IGNNE_MASK;
/*
* We get here in response to a write to port F0h. The chipset should
@@ -4619,7 +4619,11 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x0a: /* grp d9/2 */
switch (rm) {
case 0: /* fnop */
- /* check exceptions (FreeBSD FPU probe) */
+ /*
+ * check exceptions (FreeBSD FPU probe)
+ * needs to be treated as I/O because of ferr_irq
+ */
+ translator_io_start(&s->base);
gen_helper_fwait(cpu_env);
update_fip = false;
break;
@@ -5548,6 +5552,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
(HF_MP_MASK | HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
} else {
+ /* needs to be treated as I/O because of ferr_irq */
+ translator_io_start(&s->base);
gen_helper_fwait(cpu_env);
}
break;