@@ -1034,6 +1034,7 @@ void ct3_realize(PCIDevice *pci_dev, Error **errp)
goto err_release_cdat;
}
}
+
return;
err_release_cdat:
@@ -1249,6 +1250,7 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
CXLType3Dev *ct3d = CXL_TYPE3(d);
+ CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
uint64_t dpa_offset = 0;
AddressSpace *as = NULL;
int res;
@@ -1259,6 +1261,11 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
return MEMTX_ERROR;
}
+ if (cvc->mhd_access_valid &&
+ !cvc->mhd_access_valid(d, dpa_offset, size)) {
+ return MEMTX_ERROR;
+ }
+
if (sanitize_running(&ct3d->cci)) {
qemu_guest_getrandom_nofail(data, size);
return MEMTX_OK;
@@ -1270,6 +1277,7 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
unsigned size, MemTxAttrs attrs)
{
CXLType3Dev *ct3d = CXL_TYPE3(d);
+ CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
uint64_t dpa_offset = 0;
AddressSpace *as = NULL;
int res;
@@ -1279,6 +1287,12 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
if (res) {
return MEMTX_ERROR;
}
+
+ if (cvc->mhd_access_valid &&
+ !cvc->mhd_access_valid(d, dpa_offset, size)) {
+ return MEMTX_ERROR;
+ }
+
if (sanitize_running(&ct3d->cci)) {
return MEMTX_OK;
}
@@ -2106,6 +2120,7 @@ static void ct3_class_init(ObjectClass *oc, void *data)
cvc->get_lsa = get_lsa;
cvc->set_lsa = set_lsa;
cvc->set_cacheline = set_cacheline;
+ cvc->mhd_access_valid = NULL;
}
static const TypeInfo ct3d_info = {
@@ -506,6 +506,9 @@ struct CXLType3Class {
void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
uint64_t offset);
bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data);
+
+ /* Multi-headed Device */
+ bool (*mhd_access_valid)(PCIDevice *d, uint64_t addr, unsigned int size);
};
struct CSWMBCCIDev {
When memory accesses are made, some MHSLD's would validate the address is within the scope of allocated sections. To do this, the base device must call an optional function set by inherited devices. Signed-off-by: Gregory Price <gregory.price@memverge.com> --- hw/mem/cxl_type3.c | 15 +++++++++++++++ include/hw/cxl/cxl_device.h | 3 +++ 2 files changed, 18 insertions(+)