Message ID | 20230901194627.1214811-21-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: 'max' CPU, detect user choice in TCG | expand |
On Fri, Sep 01, 2023 at 04:46:26PM -0300, Daniel Henrique Barboza wrote: > Enabling RVG will enable a set of extensions that we're not checking if > the user was okay enabling or not. And in this case we want to error > out, instead of ignoring, otherwise we will be inconsistent enabling RVG > without all its extensions. > > After this patch, disabling ifencei or icsr while enabling RVG will > result in error: > > $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic > qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 78382cb5f2..be1c028095 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && > riscv_has_ext(env, RVD) && > cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > + > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && > + !cpu->cfg.ext_icsr) { > + error_setg(errp, "RVG requires Zicsr but user set Zicsr to false"); > + return; > + } > + > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && > + !cpu->cfg.ext_ifencei) { > + error_setg(errp, "RVG requires Zifencei but user set " > + "Zifencei to false"); > + return; > + } > + > warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > - cpu->cfg.ext_icsr = true; > - cpu->cfg.ext_ifencei = true; > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); > > env->misa_ext |= RVI | RVM | RVA | RVF | RVD; > env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; > -- > 2.41.0 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 78382cb5f2..be1c028095 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to false"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_icsr = true; - cpu->cfg.ext_ifencei = true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); env->misa_ext |= RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;