From patchwork Fri Sep 1 19:46:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1828964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=NklMquHB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RcpWC54Zgz1ygF for ; Sat, 2 Sep 2023 05:48:55 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qcA89-0000VL-FS; Fri, 01 Sep 2023 15:48:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qcA6z-00080b-Lc for qemu-devel@nongnu.org; Fri, 01 Sep 2023 15:47:25 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qcA6w-0003H7-7P for qemu-devel@nongnu.org; Fri, 01 Sep 2023 15:47:21 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1c8d895a602so1514578fac.2 for ; Fri, 01 Sep 2023 12:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693597636; x=1694202436; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q6U/kJmT8i79eDIx8//Bo6UHXfVCePxHVAlASyqB6rg=; b=NklMquHBS6DmPZhQBQUZjyJH31dO5pxnK1OuiBZDq4KfYVqg9vS0xCjgNMcRAyVZfF jcP4JtSNQYi5mdXnafw7c6nTSj2IoR8VAYrqp6LMVJvO7qUxA2l95Csse3syjW1Cwhl+ M4kr3OJXiPmA1IBuKd8FPtNmud//Z3B9h+DGAqPXeuFRGNYw10KUBFHxoq3/cjuM/O1j YV3/dSr4rAC5DRpNopSqB1gu94PWGFzgJPfTArOYtDbD+sfWOKHR88jdwvZ24c0FagR+ o3OfijGRZDSA+w9WcaGEWdjjn0yb9SP94gyByfXV5GVqGZAeJShBc3S4BFK2tlVlSUK2 rixA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693597636; x=1694202436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q6U/kJmT8i79eDIx8//Bo6UHXfVCePxHVAlASyqB6rg=; b=J/mle0LH+pnDhjIs032ilrGClKhA5GoVgqwbAEUWSmnANJv3HTJ3vKsdgsJb4pwzx3 nvOBHImrsOnDWuHXzdr6MGPnSFI0PEpmP831nYueK/Zp2FGkVz95dteBRry4p8mV7yHT DJvEwsXqw/mymp0piAMMh7tlAvzUZIgQWDnTy0jALlRC2nO5bfSEV2w9SXanHqOa3VUp 8FDYjRk96X8YQVicVrS63DVq/Q5aMUHHDUkeAOjiL5wgFmA6SHgNhpDsQ9Wqkv+UtMUo 3I9mOItZ1S8lBqD6sXq2uDKG0IBosPEwo5HwDll/HQHRD6rHvkpUkTVdHr7t9hgW0qzl mdfw== X-Gm-Message-State: AOJu0Yy+FC/qNt3uC+FtgVcipBWUMRyCYzKTcJFj3ODKTmgLn3zexwTR i9YU7lMoWULsjHeCjbdeYcDrSOa8IluxZpRRezE= X-Google-Smtp-Source: AGHT+IGCqXPjvCr3fiX7JRXdG0KLJYZLSdMCigpsIAzRriouv6WRWq5U3nKQVBi7AM1I6s9hkp+vtg== X-Received: by 2002:a05:6870:35cd:b0:1ba:3ff0:4934 with SMTP id c13-20020a05687035cd00b001ba3ff04934mr3725930oak.12.1693597636642; Fri, 01 Sep 2023 12:47:16 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id h187-20020a4a5ec4000000b00565d41ba4d0sm2303002oob.35.2023.09.01.12.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Sep 2023 12:47:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Date: Fri, 1 Sep 2023 16:46:19 -0300 Message-ID: <20230901194627.1214811-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230901194627.1214811-1-dbarboza@ventanamicro.com> References: <20230901194627.1214811-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dae259e02..03e936348a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -162,18 +162,17 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; -static bool isa_ext_is_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata) +static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; return *ext_enabled; } -static void isa_ext_update_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata, bool en) +static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, + bool en) { - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; *ext_enabled = en; } @@ -1045,9 +1044,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) /* Force disable extensions if priv spec version does not match */ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); + isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, + false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", @@ -2346,7 +2346,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int i; for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old = new;