Message ID | 20230825130853.511782-11-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: split TCG/KVM accelerators from cpu.c | expand |
On Fri, Aug 25, 2023 at 10:08:43AM -0300, Daniel Henrique Barboza wrote: > We'll introduce the KVM accelerator class with a 'cpu_instance_init' > implementation that is going to be invoked during the common > riscv_cpu_post_init() (via accel_cpu_instance_init()). This > instance_init will execute KVM exclusive code that TCG doesn't care > about, such as adding KVM specific properties, initing registers using a > KVM scratch CPU and so on. > > The core of the forementioned cpu_instance_init impl is the current > riscv_cpu_add_kvm_properties() that is being used by the common code via > riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together > will all the relevant artifacts, exporting and renaming it to > kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now. > > To make this work we'll need to export riscv_cpu_extensions, > riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as > well. The TCG accelerator will also need to access those in the near > future so this export will benefit us in the long run. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 87 +++------------------------------------- > target/riscv/cpu.h | 14 +++++++ > target/riscv/kvm.c | 66 +++++++++++++++++++++++++++++- > target/riscv/kvm_riscv.h | 2 +- > 4 files changed, 86 insertions(+), 83 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4eda853f1d..58b0ef2af8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1344,7 +1344,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > MISA_CFG(RVG, false), > }; > > -static void riscv_cpu_add_misa_properties(Object *cpu_obj) > +void riscv_cpu_add_misa_properties(Object *cpu_obj) > { > int i; > > @@ -1371,17 +1371,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) > } > } > > -typedef struct RISCVCPUMultiExtConfig { > - const char *name; > - uint32_t offset; > - bool enabled; > -} RISCVCPUMultiExtConfig; > - > #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ > {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ > .enabled = _defval} > > -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), > @@ -1441,7 +1435,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), > MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), > MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), > @@ -1459,7 +1453,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > }; > > /* These are experimental so mark with 'x-' */ > -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false), > > /* ePMP 0.9.3 */ > @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static Property riscv_cpu_options[] = { > +Property riscv_cpu_options[] = { > DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > @@ -1548,25 +1542,6 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj, > multi_cfg->enabled); > } > > -#ifndef CONFIG_USER_ONLY > -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, > - const char *name, > - void *opaque, Error **errp) > -{ > - const char *propname = opaque; > - bool value; > - > - if (!visit_type_bool(v, name, &value, errp)) { > - return; > - } > - > - if (value) { > - error_setg(errp, "extension %s is not available with KVM", > - propname); > - } > -} > -#endif > - > static void riscv_cpu_add_multiext_prop_array(Object *obj, > const RISCVCPUMultiExtConfig *array) > { > @@ -1577,56 +1552,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj, > } > } > > -#ifndef CONFIG_USER_ONLY > -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) > -{ > - /* Check if KVM created the property already */ > - if (object_property_find(obj, prop_name)) { > - return; > - } > - > - /* > - * Set the default to disabled for every extension > - * unknown to KVM and error out if the user attempts > - * to enable any of them. > - */ > - object_property_add(obj, prop_name, "bool", > - NULL, cpu_set_cfg_unavailable, > - NULL, (void *)prop_name); > -} > - > -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, > - const RISCVCPUMultiExtConfig *array) > -{ > - const RISCVCPUMultiExtConfig *prop; > - > - for (prop = array; prop && prop->name; prop++) { > - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); > - } > -} > - > -static void riscv_cpu_add_kvm_properties(Object *obj) > -{ > - Property *prop; > - DeviceState *dev = DEVICE(obj); > - > - kvm_riscv_init_user_properties(obj); > - riscv_cpu_add_misa_properties(obj); > - > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); > - > - for (prop = riscv_cpu_options; prop && prop->name; prop++) { > - /* Check if KVM created the property already */ > - if (object_property_find(obj, prop->name)) { > - continue; > - } > - qdev_property_add_static(dev, prop); > - } > -} > -#endif > - > /* > * Add CPU properties with user-facing flags. > * > @@ -1639,7 +1564,7 @@ static void riscv_cpu_add_user_properties(Object *obj) > riscv_add_satp_mode_properties(obj); > > if (kvm_enabled()) { > - riscv_cpu_add_kvm_properties(obj); > + kvm_riscv_cpu_add_kvm_properties(obj); > return; > } > #endif > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 2ac00a0304..b9c4bea3f7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -22,6 +22,7 @@ > > #include "hw/core/cpu.h" > #include "hw/registerfields.h" > +#include "hw/qdev-properties.h" > #include "exec/cpu-defs.h" > #include "qemu/cpu-float.h" > #include "qom/object.h" > @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); > int cpu_cfg_ext_get_min_version(uint32_t ext_offset); > void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); > > +typedef struct RISCVCPUMultiExtConfig { > + const char *name; > + uint32_t offset; > + bool enabled; > +} RISCVCPUMultiExtConfig; > + > +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; > +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > +extern Property riscv_cpu_options[]; > + > +void riscv_cpu_add_misa_properties(Object *cpu_obj); > + > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 59004caa8e..7e67121456 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -338,6 +338,50 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) > } > } > > +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, > + const char *name, > + void *opaque, Error **errp) > +{ > + const char *propname = opaque; > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + if (value) { > + error_setg(errp, "extension %s is not available with KVM", > + propname); > + } > +} > + > +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) > +{ > + /* Check if KVM created the property already */ > + if (object_property_find(obj, prop_name)) { > + return; > + } > + > + /* > + * Set the default to disabled for every extension > + * unknown to KVM and error out if the user attempts > + * to enable any of them. > + */ > + object_property_add(obj, prop_name, "bool", > + NULL, cpu_set_cfg_unavailable, > + NULL, (void *)prop_name); > +} > + > +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, > + const RISCVCPUMultiExtConfig *array) > +{ > + const RISCVCPUMultiExtConfig *prop; > + > + for (prop = array; prop && prop->name; prop++) { > + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); > + } > +} > + > static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > { > int i; > @@ -747,7 +791,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) > } > } > > -void kvm_riscv_init_user_properties(Object *cpu_obj) > +static void riscv_init_user_properties(Object *cpu_obj) > { > RISCVCPU *cpu = RISCV_CPU(cpu_obj); > KVMScratchCPU kvmcpu; > @@ -1218,6 +1262,26 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); > } > > +void kvm_riscv_cpu_add_kvm_properties(Object *obj) > +{ > + DeviceState *dev = DEVICE(obj); > + > + riscv_init_user_properties(obj); > + riscv_cpu_add_misa_properties(obj); > + > + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); > + > + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { > + /* Check if KVM created the property already */ > + if (object_property_find(obj, prop->name)) { > + continue; > + } > + qdev_property_add_static(dev, prop); > + } > +} > + > static void riscv_host_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h > index 7d4b7c60e2..81e08b8359 100644 > --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -19,7 +19,7 @@ > #ifndef QEMU_KVM_RISCV_H > #define QEMU_KVM_RISCV_H > > -void kvm_riscv_init_user_properties(Object *cpu_obj); > +void kvm_riscv_cpu_add_kvm_properties(Object *obj); > void kvm_riscv_reset_vcpu(RISCVCPU *cpu); > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); > void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > -- > 2.41.0 > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4eda853f1d..58b0ef2af8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1344,7 +1344,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVG, false), }; -static void riscv_cpu_add_misa_properties(Object *cpu_obj) +void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i; @@ -1371,17 +1371,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) } } -typedef struct RISCVCPUMultiExtConfig { - const char *name; - uint32_t offset; - bool enabled; -} RISCVCPUMultiExtConfig; - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ .enabled = _defval} -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1441,7 +1435,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1459,7 +1453,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { }; /* These are experimental so mark with 'x-' */ -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false), /* ePMP 0.9.3 */ @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { DEFINE_PROP_END_OF_LIST(), }; -static Property riscv_cpu_options[] = { +Property riscv_cpu_options[] = { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), @@ -1548,25 +1542,6 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj, multi_cfg->enabled); } -#ifndef CONFIG_USER_ONLY -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - const char *propname = opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - error_setg(errp, "extension %s is not available with KVM", - propname); - } -} -#endif - static void riscv_cpu_add_multiext_prop_array(Object *obj, const RISCVCPUMultiExtConfig *array) { @@ -1577,56 +1552,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj, } } -#ifndef CONFIG_USER_ONLY -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) -{ - /* Check if KVM created the property already */ - if (object_property_find(obj, prop_name)) { - return; - } - - /* - * Set the default to disabled for every extension - * unknown to KVM and error out if the user attempts - * to enable any of them. - */ - object_property_add(obj, prop_name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop_name); -} - -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *array) -{ - const RISCVCPUMultiExtConfig *prop; - - for (prop = array; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } -} - -static void riscv_cpu_add_kvm_properties(Object *obj) -{ - Property *prop; - DeviceState *dev = DEVICE(obj); - - kvm_riscv_init_user_properties(obj); - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); - - for (prop = riscv_cpu_options; prop && prop->name; prop++) { - /* Check if KVM created the property already */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } -} -#endif - /* * Add CPU properties with user-facing flags. * @@ -1639,7 +1564,7 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_add_satp_mode_properties(obj); if (kvm_enabled()) { - riscv_cpu_add_kvm_properties(obj); + kvm_riscv_cpu_add_kvm_properties(obj); return; } #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac00a0304..b9c4bea3f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -22,6 +22,7 @@ #include "hw/core/cpu.h" #include "hw/registerfields.h" +#include "hw/qdev-properties.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qom/object.h" @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern Property riscv_cpu_options[]; + +void riscv_cpu_add_misa_properties(Object *cpu_obj); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 59004caa8e..7e67121456 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -338,6 +338,50 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) } } +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + const char *propname = opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + error_setg(errp, "extension %s is not available with KVM", + propname); + } +} + +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) +{ + /* Check if KVM created the property already */ + if (object_property_find(obj, prop_name)) { + return; + } + + /* + * Set the default to disabled for every extension + * unknown to KVM and error out if the user attempts + * to enable any of them. + */ + object_property_add(obj, prop_name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop_name); +} + +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *array) +{ + const RISCVCPUMultiExtConfig *prop; + + for (prop = array; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -747,7 +791,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) } } -void kvm_riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu = RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -1218,6 +1262,26 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); } +void kvm_riscv_cpu_add_kvm_properties(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + riscv_init_user_properties(obj); + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { + /* Check if KVM created the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); + } +} + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 7d4b7c60e2..81e08b8359 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,7 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H -void kvm_riscv_init_user_properties(Object *cpu_obj); +void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
We'll introduce the KVM accelerator class with a 'cpu_instance_init' implementation that is going to be invoked during the common riscv_cpu_post_init() (via accel_cpu_instance_init()). This instance_init will execute KVM exclusive code that TCG doesn't care about, such as adding KVM specific properties, initing registers using a KVM scratch CPU and so on. The core of the forementioned cpu_instance_init impl is the current riscv_cpu_add_kvm_properties() that is being used by the common code via riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together will all the relevant artifacts, exporting and renaming it to kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now. To make this work we'll need to export riscv_cpu_extensions, riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as well. The TCG accelerator will also need to access those in the near future so this export will benefit us in the long run. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 87 +++------------------------------------- target/riscv/cpu.h | 14 +++++++ target/riscv/kvm.c | 66 +++++++++++++++++++++++++++++- target/riscv/kvm_riscv.h | 2 +- 4 files changed, 86 insertions(+), 83 deletions(-)