From patchwork Thu Aug 24 14:29:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 1825437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=MCsVpczd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RWly65Yr5z1yg8 for ; Fri, 25 Aug 2023 00:36:14 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZBNL-00026c-0X; Thu, 24 Aug 2023 10:31:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZBNE-0001id-QU for qemu-devel@nongnu.org; Thu, 24 Aug 2023 10:31:49 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qZBNB-0000uu-8e for qemu-devel@nongnu.org; Thu, 24 Aug 2023 10:31:48 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-56a3e6bce68so2771423a12.1 for ; Thu, 24 Aug 2023 07:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692887504; x=1693492304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fktVFjxajwjIn3pW+eH8a+AlgKI895FkdjadjybOSXU=; b=MCsVpczdJaGdPSY+cmvCgwp/JQqtwZ7vnGIF0yvtVDP13h6BlIqEqEQR1MvV99lpjZ 7gKdt2YIJmocCCnxv+zmKrLL0AwBjn0wID5/8SLCFLecl8aITgJu3kzeQkvuvDVTzmrb xv3m6SPHCy86KTWG2hOgZsw1tbUr7pwi7Id6l2mmlb9c74jGqHbeKSoZCY9vZPVyfhxS 73T+rQAe43MJ0iybGIsXSS8n9Id4eLzjgqyDkauvzIOnGW89px9clhIVEgpv129pYVuB u/mU+dJ+2jDjtwn9oZO3SNNjsD4cVP6waY/cWCDyjHJYf20uxutG1/Yt9QaRZwuKcazt QHZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692887504; x=1693492304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fktVFjxajwjIn3pW+eH8a+AlgKI895FkdjadjybOSXU=; b=D3FUiIOeMERbuRU8ZZ9/INbWJkf59kUeXPCD/PqH9e4J0MJAe69nXA3SwJckZYZksd BOVE7NlYsOZFg8fyZ450udUE9tpWoHbqCd0HLfX4q5hpv5hHKnPyJQ6BajUcJlJZY0tz 24zs3X7gt4xVTvM5lq4iL6+L+fqaLhaVNVsmYHIbs/dEMG1MTuf6A5MYu+4Z2vyohKsn TBv49UNTTG98q0Z9ptWQCTBqzTTDfLi0TIDnOrABVcF5D2ZxFKKXPoXylHtOqnVyrg6A OS6cpUH5S5USWv4SNXdPuSicX95RQxCNx+yuYwnLjEknfl6vh2Pwf7YHMU1dwRMYB5PR DsBA== X-Gm-Message-State: AOJu0YwGY0JE/zhxGZkuSmsFVjtGCBjr66lUVI84s+FFG0EoGMWN1mOb zsceClsJNR/zsUpggxuHuydLhA== X-Google-Smtp-Source: AGHT+IELKloQmE1YG6iqHHWHxrC4vT7e/w/r3cwI3y/EkCBNXzyWtNVS9yC8EoO5IcTUx4AxB7NeEw== X-Received: by 2002:a17:90b:1d8b:b0:263:829:2de with SMTP id pf11-20020a17090b1d8b00b00263082902demr12697536pjb.2.1692887503813; Thu, 24 Aug 2023 07:31:43 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.191.205]) by smtp.gmail.com with ESMTPSA id n6-20020a17090a2bc600b00262fc3d911esm1666864pje.28.2023.08.24.07.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 07:31:41 -0700 (PDT) From: Sunil V L To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Shannon Zhao , Peter Maydell , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v2 10/12] hw/riscv/virt: Update GPEX MMIO related properties Date: Thu, 24 Aug 2023 19:59:40 +0530 Message-Id: <20230824142942.3983650-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230824142942.3983650-1-sunilvl@ventanamicro.com> References: <20230824142942.3983650-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=sunilvl@ventanamicro.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Update the GPEX host bridge properties related to MMIO ranges with values set for the virt machine. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L --- hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++------------- include/hw/riscv/virt.h | 1 + 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7b65a847e2..f2b5e8338d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, - hwaddr ecam_base, hwaddr ecam_size, - hwaddr mmio_base, hwaddr mmio_size, - hwaddr high_mmio_base, - hwaddr high_mmio_size, - hwaddr pio_base, - DeviceState *irqchip) + DeviceState *irqchip, + RISCVVirtState *s) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; + hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; + hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; + hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; + hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; + hwaddr high_mmio_base = virt_high_pcie_memmap.base; + hwaddr high_mmio_size = virt_high_pcie_memmap.size; + hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; + hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; qemu_irq irq; int i; dev = qdev_new(TYPE_GPEX_HOST); + /* Set GPEX object properties for the virt machine */ + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, + ecam_base, NULL); + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, + ecam_size, NULL); + object_property_set_uint(OBJECT(GPEX_HOST(dev)), + PCI_HOST_BELOW_4G_MMIO_BASE, + mmio_base, NULL); + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, + mmio_size, NULL); + object_property_set_uint(OBJECT(GPEX_HOST(dev)), + PCI_HOST_ABOVE_4G_MMIO_BASE, + high_mmio_base, NULL); + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, + high_mmio_size, NULL); + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, + pio_base, NULL); + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, + pio_size, NULL); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); ecam_alias = g_new0(MemoryRegion, 1); @@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); } + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; return dev; } @@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } - gpex_pcie_init(system_memory, - memmap[VIRT_PCIE_ECAM].base, - memmap[VIRT_PCIE_ECAM].size, - memmap[VIRT_PCIE_MMIO].base, - memmap[VIRT_PCIE_MMIO].size, - virt_high_pcie_memmap.base, - virt_high_pcie_memmap.size, - memmap[VIRT_PCIE_PIO].base, - pcie_irqchip); + gpex_pcie_init(system_memory, pcie_irqchip, s); create_platform_bus(s, mmio_irqchip); diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 5b03575ed3..f89790fd58 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -61,6 +61,7 @@ struct RISCVVirtState { char *oem_table_id; OnOffAuto acpi; const MemMapEntry *memmap; + struct GPEXHost *gpex_host; }; enum {