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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Jiaxun Yang , Song Gao Subject: [PATCH 1/6] target/arm: Use hswap_i32() in VREV/SMLAD opcodes Date: Tue, 22 Aug 2023 13:01:24 +0200 Message-ID: <20230822110129.41022-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822110129.41022-1-philmd@linaro.org> References: <20230822110129.41022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it as gen_swap_half(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a32.h | 6 ------ target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg/translate.c | 4 ++-- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 48a15379d2..0c8f408eea 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -158,10 +158,4 @@ DO_GEN_ST(32, MO_UL) /* Set NZCV flags from the high 4 bits of var. */ #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) -/* Swap low and high halfwords. */ -static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) -{ - tcg_gen_rotri_i32(dest, var, 16); -} - #endif diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 8de4ceb203..0e59b03ff9 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -2906,7 +2906,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) tcg_gen_bswap32_i32(tmp[half], tmp[half]); break; case 1: - gen_swap_half(tmp[half], tmp[half]); + tcg_gen_hswap_i32(tmp[half], tmp[half]); break; case 2: break; @@ -3516,7 +3516,7 @@ static bool trans_VREV32(DisasContext *s, arg_2misc *a) { static NeonGenOneOpFn * const fn[] = { tcg_gen_bswap32_i32, - gen_swap_half, + tcg_gen_hswap_i32, NULL, NULL, }; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 1a6938d1b3..39a42611c6 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7612,7 +7612,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) t1 = load_reg(s, a->rn); t2 = load_reg(s, a->rm); if (m_swap) { - gen_swap_half(t2, t2); + tcg_gen_hswap_i32(t2, t2); } gen_smul_dual(t1, t2); @@ -7700,7 +7700,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) t1 = load_reg(s, a->rn); t2 = load_reg(s, a->rm); if (m_swap) { - gen_swap_half(t2, t2); + tcg_gen_hswap_i32(t2, t2); } gen_smul_dual(t1, t2);