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Tue, 22 Aug 2023 00:20:55 -0700 (PDT) Received: from localhost.localdomain ([37.19.214.4]) by smtp.gmail.com with ESMTPSA id a19-20020a5d4573000000b003143add4396sm14855820wrc.22.2023.08.22.00.20.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Aug 2023 00:20:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Song Gao Cc: Jiajie Chen , Xiaojuan Yang , Huacai Chen , Richard Henderson Subject: [PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions Date: Tue, 22 Aug 2023 09:19:56 +0200 Message-ID: <20230822071959.35620-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822071405.35386-1-philmd@linaro.org> References: <20230822071405.35386-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn> --- target/loongarch/translate.h | 1 + target/loongarch/insn_trans/trans_privileged.c.inc | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 0f244cd83b..f0d7b82932 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -20,6 +20,7 @@ #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) +#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) /* * If an operation is being performed on less than TARGET_LONG_BITS, diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 684ff547a7..099cd871f0 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -437,6 +437,10 @@ static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a) TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + if (!avail_LSPW(ctx)) { + return true; + } + if (check_plv(ctx)) { return false; } @@ -450,6 +454,10 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a) TCGv src = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + if (!avail_LSPW(ctx)) { + return true; + } + if (check_plv(ctx)) { return false; }