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[176.182.122.208]) by smtp.gmail.com with ESMTPSA id 21-20020a05600c22d500b003fee777fd84sm7809383wmg.41.2023.08.21.06.00.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Aug 2023 06:00:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Song Gao , Jiajie Chen , Xiaojuan Yang , Huacai Chen , Richard Henderson Subject: [PATCH v3 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Date: Mon, 21 Aug 2023 14:59:56 +0200 Message-ID: <20230821125959.28666-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821125959.28666-1-philmd@linaro.org> References: <20230821125959.28666-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). In preparation of supporting loongarch32 cores, rename these functions using the '64' suffix. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 34d6c5a31d..6384bda1bd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -695,11 +695,6 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = { }; #endif -static gchar *loongarch_gdb_arch_name(CPUState *cs) -{ - return g_strdup("loongarch64"); -} - static void loongarch_cpu_class_init(ObjectClass *c, void *data) { LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); @@ -724,16 +719,27 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->disas_set_info = loongarch_cpu_disas_set_info; cc->gdb_read_register = loongarch_cpu_gdb_read_register; cc->gdb_write_register = loongarch_cpu_gdb_write_register; - cc->gdb_num_core_regs = 35; - cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_stop_before_watchpoint = true; - cc->gdb_arch_name = loongarch_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif } +static gchar *loongarch64_gdb_arch_name(CPUState *cs) +{ + return g_strdup("loongarch64"); +} + +static void loongarch64_cpu_class_init(ObjectClass *c, void *data) +{ + CPUClass *cc = CPU_CLASS(c); + + cc->gdb_num_core_regs = 35; + cc->gdb_core_xml_file = "loongarch-base64.xml"; + cc->gdb_arch_name = loongarch64_gdb_arch_name; +} + #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ { \ .parent = TYPE_LOONGARCH##size##_CPU, \ @@ -757,6 +763,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .parent = TYPE_LOONGARCH_CPU, .abstract = true, + .class_init = loongarch64_cpu_class_init, }, DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), };