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[176.182.122.208]) by smtp.gmail.com with ESMTPSA id f8-20020adfdb48000000b0031934b035d2sm12570855wrj.52.2023.08.21.06.00.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Aug 2023 06:00:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Song Gao , Jiajie Chen , Xiaojuan Yang , Huacai Chen Subject: [PATCH v3 1/8] target/loongarch: Log I/O write accesses to CSR registers Date: Mon, 21 Aug 2023 14:59:52 +0200 Message-ID: <20230821125959.28666-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821125959.28666-1-philmd@linaro.org> References: <20230821125959.28666-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Various CSR registers have Read/Write fields. We might want to see guest trying to change such registers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Song Gao --- target/loongarch/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ad93ecac92..7107968699 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -544,6 +544,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) static void loongarch_qemu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", + __func__, addr); } static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)