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([2602:47:d483:7301:e773:351d:2db2:8a8a]) by smtp.gmail.com with ESMTPSA id 22-20020a17090a19d600b00263d3448141sm3803713pjj.8.2023.08.11.09.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 09:51:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, pbonzini@redhat.com, philmd@linaro.org Subject: [PATCH v3 10/15] target/arm: Add isar_feature_aa32_a32 Date: Fri, 11 Aug 2023 09:50:47 -0700 Message-Id: <20230811165052.161080-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811165052.161080-1-richard.henderson@linaro.org> References: <20230811165052.161080-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a probe for whether A32 mode is supported. Fill in the field for the pre-v5 cpus. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/tcg/cpu32.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda6..41d05839a2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3462,6 +3462,11 @@ static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; } +static inline bool isar_feature_aa32_a32(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, STATE0) != 0; +} + static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 47d2e8e781..ea8ccf59a9 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -145,6 +145,8 @@ static void arm926_initfn(Object *obj) cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + /* Similarly, we need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); } static void arm946_initfn(Object *obj) @@ -158,6 +160,9 @@ static void arm946_initfn(Object *obj) cpu->midr = 0x41059461; cpu->ctr = 0x0f004006; cpu->reset_sctlr = 0x00000078; + + /* We need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); } static void arm1026_initfn(Object *obj) @@ -187,6 +192,8 @@ static void arm1026_initfn(Object *obj) cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + /* Similarly, we need to set STATE0 for A32 support. */ + cpu->isar.id_pfr0 = FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, STATE0, 1); { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */