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Fri, 11 Aug 2023 06:02:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qUOyJ-0002Ez-7V for qemu-devel@nongnu.org; Fri, 11 Aug 2023 06:02:22 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxlPAnB9ZkzoAVAA--.45869S3; Fri, 11 Aug 2023 18:02:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxTSMhB9ZkBcpUAA--.61494S8; Fri, 11 Aug 2023 18:02:15 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn, c@jia.je Subject: [PATCH v2 6/8] target/loongarch: Add avail_LAM to check atomic instructions Date: Fri, 11 Aug 2023 18:02:06 +0800 Message-Id: <20230811100208.271649-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230811100208.271649-1-gaosong@loongson.cn> References: <20230811100208.271649-1-gaosong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxTSMhB9ZkBcpUAA--.61494S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_atomic.c.inc | 12 ++++++++++++ target/loongarch/translate.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc index 194818d74d..867d09375a 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -9,6 +9,10 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv t0 = make_address_i(ctx, src1, a->imm); + if (!avail_LAM(ctx)) { + return true; + } + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); @@ -25,6 +29,10 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv t0 = tcg_temp_new(); TCGv val = tcg_temp_new(); + if (!avail_LAM(ctx)) { + return true; + } + TCGLabel *l1 = gen_new_label(); TCGLabel *done = gen_new_label(); @@ -53,6 +61,10 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); TCGv val = gpr_src(ctx, a->rk, EXT_NONE); + if (!avail_LAM(ctx)) { + return true; + } + if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) { qemu_log_mask(LOG_GUEST_ERROR, "Warning: source register overlaps destination register" diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index f0d7b82932..faf4ce87f9 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -21,6 +21,7 @@ #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) +#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) /* * If an operation is being performed on less than TARGET_LONG_BITS,