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Tue, 08 Aug 2023 11:17:19 -0700 (PDT) Received: from vineet-framework.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e5-20020a170902b78500b001a5fccab02dsm9337248pls.177.2023.08.08.11.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 11:17:19 -0700 (PDT) From: Vineet Gupta To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , Vineet Gupta Subject: [PATCH 2/2] riscv: zicond: make default Date: Tue, 8 Aug 2023 11:17:15 -0700 Message-Id: <20230808181715.436395-2-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808181715.436395-1-vineetg@rivosinc.com> References: <20230808181715.436395-1-vineetg@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=vineetg@rivosinc.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Again this helps with better testing and something qemu has been doing with newer features anyways. Signed-off-by: Vineet Gupta --- target/riscv/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 022bd9d01223..e6e28414b223 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.ext_xtheadbs = true; cpu->cfg.ext_xtheadcmo = true; cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_zicond = false; cpu->cfg.ext_xtheadfmemidx = true; cpu->cfg.ext_xtheadmac = true; cpu->cfg.ext_xtheadmemidx = true; @@ -483,6 +484,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) cpu->cfg.ext_zbc = true; cpu->cfg.ext_zbs = true; cpu->cfg.ext_XVentanaCondOps = true; + cpu->cfg.ext_zicond = false; cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; cpu->cfg.marchid = VEYRON_V1_MARCHID; @@ -1816,7 +1818,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), - DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false), + DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, true), /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),