@@ -4,3 +4,4 @@ TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+CONFIG_NATIVE_CALL=y
@@ -5,3 +5,4 @@ TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+CONFIG_NATIVE_CALL=y
@@ -25,6 +25,7 @@
#include "arm_ldst.h"
#include "semihosting/semihost.h"
#include "cpregs.h"
+#include "native/native.h"
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
@@ -2400,6 +2401,19 @@ static bool trans_HLT(DisasContext *s, arg_i *a)
* it is required for halting debug disabled: it will UNDEF.
* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
*/
+ if (native_bypass_enabled() && (a->imm == 0xffff)) {
+ TCGv_i64 arg1 = tcg_temp_new_i64();
+ TCGv_i64 arg2 = tcg_temp_new_i64();
+ TCGv_i64 arg3 = tcg_temp_new_i64();
+ TCGv_i64 ret = tcg_temp_new_i64();
+ const char *fun_name = lookup_symbol((s->base.pc_next) & 0xfff);
+ tcg_gen_mov_i64(arg1, cpu_reg(s, 0));
+ tcg_gen_mov_i64(arg2, cpu_reg(s, 1));
+ tcg_gen_mov_i64(arg3, cpu_reg(s, 2));
+ gen_native_call_i64(fun_name, ret, arg1, arg2, arg3);
+ tcg_gen_mov_i64(cpu_reg(s, 0), ret);
+ return true;
+ }
if (semihosting_enabled(s->current_el == 0) && a->imm == 0xf000) {
gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else {
@@ -27,6 +27,7 @@
#include "arm_ldst.h"
#include "semihosting/semihost.h"
#include "cpregs.h"
+#include "native/native.h"
#include "exec/helper-proto.h"
#define HELPER_H "helper.h"
@@ -1139,6 +1140,16 @@ static inline void gen_hlt(DisasContext *s, int imm)
* semihosting, to provide some semblance of security
* (and for consistency with our 32-bit semihosting).
*/
+ if (native_bypass_enabled() && (imm == 0xffff)) {
+ TCGv_i32 arg1 = load_reg(s, 0);
+ TCGv_i32 arg2 = load_reg(s, 1);
+ TCGv_i32 arg3 = load_reg(s, 2);
+ TCGv_i32 ret = tcg_temp_new_i32();
+ const char *fun_name = lookup_symbol((s->base.pc_next) & 0xfff);
+ gen_native_call_i32(fun_name, ret, arg1, arg2, arg3);
+ store_reg(s, 0, ret);
+ return;
+ }
if (semihosting_enabled(s->current_el == 0) &&
(imm == (s->thumb ? 0x3c : 0xf000))) {
gen_exception_internal_insn(s, EXCP_SEMIHOST);
This commit introduces support for native library calls on the arm target. When special instructions reserved for native calls are encountered, the code now performs address translation and generates the corresponding native call. Signed-off-by: Yeqi Fu <fufuyqqqqqq@gmail.com> --- configs/targets/aarch64-linux-user.mak | 1 + configs/targets/arm-linux-user.mak | 1 + target/arm/tcg/translate-a64.c | 14 ++++++++++++++ target/arm/tcg/translate.c | 11 +++++++++++ 4 files changed, 27 insertions(+)