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Tue, 08 Aug 2023 01:35:19 -0700 (PDT) Received: from voyager.lan ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id n9-20020a170902e54900b001b8062c1db3sm8368112plf.82.2023.08.08.01.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 01:35:18 -0700 (PDT) From: Joel Stanley To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= , Nicholas Piggin Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-8.2 1/3] pnv/lpc: Place mmio regs in their own memory region Date: Tue, 8 Aug 2023 18:04:43 +0930 Message-Id: <20230808083445.4613-2-joel@jms.id.au> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230808083445.4613-1-joel@jms.id.au> References: <20230808083445.4613-1-joel@jms.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=joel.stan@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The P9 and P10 models re-used the xscom_regs memory region for the mmio access, which is confusing. Add a separate memory region in preparation for enabling both xscom and mmio access. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_lpc.h | 3 ++- hw/ppc/pnv.c | 4 ++-- hw/ppc/pnv_lpc.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 5d22c4557041..3000964f8999 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -81,8 +81,9 @@ struct PnvLpcController { uint32_t lpc_hc_irqstat; uint32_t lpc_hc_error_addr; - /* XSCOM registers */ + /* Registers */ MemoryRegion xscom_regs; + MemoryRegion mmio_regs; /* PSI to generate interrupts */ qemu_irq psi_irq; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index eb54f93986df..afdaa25c2b26 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1565,7 +1565,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) return; } memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), - &chip9->lpc.xscom_regs); + &chip9->lpc.mmio_regs); chip->fw_mr = &chip9->lpc.isa_fw; chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", @@ -1784,7 +1784,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) return; } memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), - &chip10->lpc.xscom_regs); + &chip10->lpc.mmio_regs); chip->fw_mr = &chip10->lpc.isa_fw; chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index d692858bee78..caf5e10a5f96 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -664,7 +664,7 @@ static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp) } /* P9 uses a MMIO region */ - memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, + memory_region_init_io(&lpc->mmio_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, lpc, "lpcm", PNV9_LPCM_SIZE); }