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Iglesias" , Brian Cain , Song Gao , Xiaojuan Yang , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz , Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Anton Kochkov , Akihiko Odaki Subject: [PATCH v2 09/24] target/riscv: Use GDBFeature for dynamic XML Date: Wed, 2 Aug 2023 17:45:57 +0900 Message-ID: <20230802084614.23619-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230802084614.23619-1-akihiko.odaki@daynix.com> References: <20230802084614.23619-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::433; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu.c | 4 ++-- target/riscv/gdbstub.c | 25 ++++++++++++++----------- 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..f67751d5b7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -391,8 +391,8 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPURISCVState env; - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36de35270d..ceca40cdd9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1962,9 +1962,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) RISCVCPU *cpu = RISCV_CPU(cs); if (strcmp(xmlname, "riscv-csr.xml") == 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 524bede865..70c60ad8b1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -212,7 +212,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) return 0; } -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -252,24 +252,27 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) g_string_append_printf(s, ""); - cpu->dyn_csr_xml = g_string_free(s, false); + cpu->dyn_csr_feature.num_regs = CSR_TABLE_SIZE; + cpu->dyn_csr_feature.xmlname = "riscv-csr.xml"; + cpu->dyn_csr_feature.xml = g_string_free(s, false); #if !defined(CONFIG_USER_ONLY) env->debugger = false; #endif - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) { RISCVCPU *cpu = RISCV_CPU(cs); GString *s = g_string_new(NULL); g_autoptr(GString) ts = g_string_new(""); int reg_width = cpu->cfg.vlen; - int num_regs = 0; int i; + cpu->dyn_vreg_feature.num_regs = 32; + g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); @@ -293,19 +296,19 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) g_string_append(s, ""); /* Define vector registers */ - for (i = 0; i < 32; i++) { + for (i = 0; i < cpu->dyn_vreg_feature.num_regs; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - num_regs++; } g_string_append_printf(s, ""); - cpu->dyn_vreg_xml = g_string_free(s, false); - return num_regs; + cpu->dyn_vreg_feature.xmlname = "riscv-vector.xml"; + cpu->dyn_vreg_feature.xml = g_string_free(s, false); + return &cpu->dyn_vreg_feature; } void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -323,7 +326,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg), + ricsv_gen_dynamic_vector_feature(cs, base_reg)->num_regs, "riscv-vector.xml", 0); } switch (env->misa_mxl_max) { @@ -345,7 +348,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) if (cpu->cfg.ext_icsr) { int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs, base_reg)->num_regs, "riscv-csr.xml", 0); } }