@@ -157,8 +157,10 @@ struct CPUClass {
int64_t (*get_arch_id)(CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
vaddr (*get_pc)(CPUState *cpu);
- int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
- int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
+ int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+ int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
const GDBFeature *gdb_core_feature;
@@ -279,8 +279,10 @@ bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
-int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
#define cpu_list alpha_cpu_list
@@ -1128,8 +1128,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
#endif /* !CONFIG_USER_ONLY */
-int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+
+int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
@@ -1137,8 +1140,10 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
#ifdef TARGET_AARCH64
-int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
@@ -157,8 +157,10 @@ extern const struct VMStateDescription vms_avr_cpu;
void avr_cpu_do_interrupt(CPUState *cpu);
bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
int avr_print_insn(bfd_vma addr, disassemble_info *info);
vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
@@ -198,9 +198,12 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
-int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void cris_initialize_tcg(void);
void cris_initialize_crisv10_tcg(void);
@@ -31,8 +31,10 @@
} \
} while (0)
-int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n);
int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n);
@@ -321,8 +321,10 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
void cpu_hppa_change_prot_id(CPUHPPAState *env);
#endif
-int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
#ifndef CONFIG_USER_ONLY
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
@@ -2057,8 +2057,10 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
-int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@@ -77,8 +77,10 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
uint64_t read_fcc(CPULoongArchState *env);
void write_fcc(CPULoongArchState *env, uint64_t val);
-int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
-int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml);
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml);
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
#endif
@@ -179,8 +179,10 @@ bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
@@ -368,8 +368,10 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);
@@ -92,8 +92,10 @@ extern const char fregnames[32][4];
extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;
-int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
@@ -312,8 +312,10 @@ struct ArchCPU {
void cpu_openrisc_list(void);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void openrisc_translate_init(void);
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
@@ -1375,10 +1375,14 @@ static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
#endif /* CONFIG_USER_ONLY */
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
-int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
+int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
+int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
#ifndef CONFIG_USER_ONLY
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void ppc_gdb_gen_spr_feature(PowerPCCPU *cpu);
@@ -421,8 +421,10 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
-int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
uint8_t riscv_cpu_default_priority(int irq);
uint64_t riscv_cpu_all_pending(CPURISCVState *env);
@@ -126,8 +126,10 @@ bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void rx_translate_init(void);
void rx_cpu_list(void);
@@ -316,8 +316,10 @@ uint16_t float128_dcmask(CPUS390XState *env, float128 f1);
/* gdbstub.c */
-int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
void s390_cpu_gdb_init(CPUState *cs);
@@ -214,8 +214,10 @@ struct ArchCPU {
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
@@ -573,8 +573,10 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
void sparc_cpu_do_interrupt(CPUState *cpu);
-int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx,
@@ -361,8 +361,10 @@ enum {
uint32_t psw_read(CPUTriCoreState *env);
void psw_write(CPUTriCoreState *env, uint32_t val);
-int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
-int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
+int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml);
+int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml);
void fpu_set_state(CPUTriCoreState *env);
@@ -581,8 +581,10 @@ hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
void xtensa_count_regs(const XtensaConfig *config,
unsigned *n_regs, unsigned *n_core_regs);
-int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml);
+int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml);
G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
@@ -423,7 +423,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
- return cc->gdb_read_register(cpu, buf, reg);
+ return cc->gdb_read_register(cpu, buf, reg, gdb_has_xml);
}
for (r = cpu->gdb_regs; r; r = r->next) {
@@ -441,7 +441,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
- return cc->gdb_write_register(cpu, mem_buf, reg);
+ return cc->gdb_write_register(cpu, mem_buf, reg, gdb_has_xml);
}
for (r = cpu->gdb_regs; r; r = r->next) {
@@ -89,12 +89,14 @@ void cpu_exit(CPUState *cpu)
qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
}
-static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
+static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg,
+ bool has_xml)
{
return 0;
}
-static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
+static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg,
+ bool has_xml)
{
return 0;
}
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
@@ -57,7 +58,8 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_regl(mem_buf, val);
}
-int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
@@ -37,7 +37,8 @@ typedef struct RegisterSysregFeatureParam {
We hack round this by giving the FPA regs zero size when talking to a
newer gdb. */
-int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -48,7 +49,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
}
if (n < 24) {
/* FPA registers. */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return gdb_get_zeroes(mem_buf, 12);
@@ -56,7 +57,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
switch (n) {
case 24:
/* FPA status register. */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return gdb_get_reg32(mem_buf, 0);
@@ -72,7 +73,8 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -102,7 +104,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
if (n < 24) { /* 16-23 */
/* FPA registers (ignored). */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return 12;
@@ -110,7 +112,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
switch (n) {
case 24:
/* FPA status register (ignored). */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return 4;
@@ -22,7 +22,8 @@
#include "internals.h"
#include "gdbstub/helpers.h"
-int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -43,7 +44,8 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -21,7 +21,8 @@
#include "qemu/osdep.h"
#include "gdbstub/helpers.h"
-int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
@@ -51,7 +52,8 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
@@ -53,7 +54,8 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
@@ -88,7 +90,8 @@ int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
@@ -20,7 +20,8 @@
#include "cpu.h"
#include "internal.h"
-int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
HexagonCPU *cpu = HEXAGON_CPU(cs);
CPUHexagonState *env = &cpu->env;
@@ -40,7 +41,8 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
g_assert_not_reached();
}
-int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
HexagonCPU *cpu = HEXAGON_CPU(cs);
CPUHexagonState *env = &cpu->env;
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
@@ -146,7 +147,8 @@ int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
}
}
-int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
@@ -32,9 +32,7 @@ static const int gpr_map[16] = {
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
/*
- * Keep these in sync with assignment to
- * gdb_num_core_regs in target/i386/cpu.c
- * and with the machine description
+ * Keep these in sync with the machine description
*/
/*
@@ -96,7 +94,8 @@ static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)
return 4;
}
-int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -248,7 +247,8 @@ static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf)
return 4;
}
-int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -30,7 +30,8 @@ void write_fcc(CPULoongArchState *env, uint64_t val)
}
}
-int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
@@ -48,7 +49,8 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
@@ -48,7 +49,8 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
@@ -46,7 +46,8 @@ enum {
GDB_SP_SHR,
};
-int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -111,7 +112,8 @@ int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, val);
}
-int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -23,7 +23,8 @@
#include "gdbstub/helpers.h"
#include "fpu_helper.h"
-int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
@@ -76,7 +77,8 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
@@ -280,7 +280,8 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
info->print_insn = print_insn_nios2;
}
-static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
@@ -305,7 +306,8 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, val);
}
-static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -21,7 +21,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
@@ -46,7 +47,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -48,7 +48,7 @@ static int ppc_gdb_register_len_apple(int n)
}
}
-static int ppc_gdb_register_len(int n)
+static int ppc_gdb_register_len(int n, bool has_xml)
{
switch (n) {
case 0 ... 31:
@@ -56,7 +56,7 @@ static int ppc_gdb_register_len(int n)
return sizeof(target_ulong);
case 32 ... 63:
/* fprs */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return 8;
@@ -76,7 +76,7 @@ static int ppc_gdb_register_len(int n)
return sizeof(target_ulong);
case 70:
/* fpscr */
- if (gdb_has_xml) {
+ if (has_xml) {
return 0;
}
return sizeof(target_ulong);
@@ -118,12 +118,13 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
* the FP regs zero size when talking to a newer gdb.
*/
-int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
+int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n,
+ bool has_xml)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
uint8_t *mem_buf;
- int r = ppc_gdb_register_len(n);
+ int r = ppc_gdb_register_len(n, has_xml);
if (!r) {
return r;
@@ -168,7 +169,8 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
return r;
}
-int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
+int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n,
+ bool has_xml)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
@@ -222,11 +224,12 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
return r;
}
-int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- int r = ppc_gdb_register_len(n);
+ int r = ppc_gdb_register_len(n, has_xml);
if (!r) {
return r;
@@ -269,7 +272,8 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
return r;
}
-int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
@@ -47,7 +47,8 @@ static const struct TypeSize vec_lanes[] = {
{ "uint8", "bytes", 8, 'b' },
};
-int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -73,7 +74,8 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -19,7 +19,8 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
-int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
RXCPU *cpu = RX_CPU(cs);
CPURXState *env = &cpu->env;
@@ -51,7 +52,8 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
RXCPU *cpu = RX_CPU(cs);
CPURXState *env = &cpu->env;
@@ -28,7 +28,8 @@
#include "sysemu/hw_accel.h"
#include "sysemu/tcg.h"
-int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
S390CPU *cpu = S390_CPU(cs);
CPUS390XState *env = &cpu->env;
@@ -44,7 +45,8 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
S390CPU *cpu = S390_CPU(cs);
CPUS390XState *env = &cpu->env;
@@ -24,7 +24,8 @@
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
/* FIXME: We should use XML for this. */
-int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
@@ -74,7 +75,8 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
@@ -27,7 +27,8 @@
#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
#endif
-int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
@@ -104,7 +105,8 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
@@ -104,7 +104,8 @@ static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n,
}
-int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
@@ -119,7 +120,8 @@ int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
@@ -63,7 +63,8 @@ void xtensa_count_regs(const XtensaConfig *config,
}
}
-int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n,
+ bool has_xml)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
@@ -118,7 +119,8 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
}
}
-int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n,
+ bool has_xml)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
gdbstub has a static variable named gdb_has_xml that tells if workarounds for old GDB versions are required when manipulating registers for GDB. Now we are reusing the infrastructure to manipulate registers for plugins. Plugins will not need these workarounds even when an old GDB is attached. Converting the static variable to a function parameter would allow to apply or not to apply workarounds depending on the context. This change adds the new parameter and replaces references to gdb_has_xml with it. New code to pass different values to the functions will be added later. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> --- include/hw/core/cpu.h | 6 ++++-- target/alpha/cpu.h | 6 ++++-- target/arm/cpu.h | 13 +++++++++---- target/avr/cpu.h | 6 ++++-- target/cris/cpu.h | 9 ++++++--- target/hexagon/internal.h | 6 ++++-- target/hppa/cpu.h | 6 ++++-- target/i386/cpu.h | 6 ++++-- target/loongarch/internals.h | 6 ++++-- target/m68k/cpu.h | 6 ++++-- target/microblaze/cpu.h | 6 ++++-- target/mips/internal.h | 6 ++++-- target/openrisc/cpu.h | 6 ++++-- target/ppc/cpu.h | 12 ++++++++---- target/riscv/cpu.h | 6 ++++-- target/rx/cpu.h | 6 ++++-- target/s390x/s390x-internal.h | 6 ++++-- target/sh4/cpu.h | 6 ++++-- target/sparc/cpu.h | 6 ++++-- target/tricore/cpu.h | 6 ++++-- target/xtensa/cpu.h | 6 ++++-- gdbstub/gdbstub.c | 4 ++-- hw/core/cpu-common.c | 6 ++++-- target/alpha/gdbstub.c | 6 ++++-- target/arm/gdbstub.c | 14 ++++++++------ target/arm/gdbstub64.c | 6 ++++-- target/avr/gdbstub.c | 6 ++++-- target/cris/gdbstub.c | 9 ++++++--- target/hexagon/gdbstub.c | 6 ++++-- target/hppa/gdbstub.c | 6 ++++-- target/i386/gdbstub.c | 10 +++++----- target/loongarch/gdbstub.c | 6 ++++-- target/m68k/gdbstub.c | 6 ++++-- target/microblaze/gdbstub.c | 6 ++++-- target/mips/gdbstub.c | 6 ++++-- target/nios2/cpu.c | 6 ++++-- target/openrisc/gdbstub.c | 6 ++++-- target/ppc/gdbstub.c | 22 +++++++++++++--------- target/riscv/gdbstub.c | 6 ++++-- target/rx/gdbstub.c | 6 ++++-- target/s390x/gdbstub.c | 6 ++++-- target/sh4/gdbstub.c | 6 ++++-- target/sparc/gdbstub.c | 6 ++++-- target/tricore/gdbstub.c | 6 ++++-- target/xtensa/gdbstub.c | 6 ++++-- 45 files changed, 205 insertions(+), 110 deletions(-)