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Wed, 26 Jul 2023 11:23:00 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/6] hw/ppc: Always store the decrementer value Date: Thu, 27 Jul 2023 04:22:29 +1000 Message-Id: <20230726182230.433945-6-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230726182230.433945-1-npiggin@gmail.com> References: <20230726182230.433945-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=npiggin@gmail.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When writing a value to the decrementer that raises an exception, the irq is raised, but the value is not stored so the store doesn't appear to have changed the register when it is read again. Always store the write value to the register. Fixes: e81a982aa53 ("PPC: Clean up DECR implementation") Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index fa60f76dd4..cd1993e9c1 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -812,6 +812,11 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, return; } + /* Calculate the next timer event */ + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + next = muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND) + value; + *nextp = next; /* nextp is in timebase units */ + /* * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt. * @@ -833,11 +838,6 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, (*lower_excp)(cpu); } - /* Calculate the next timer event */ - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next = muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND) + value; - *nextp = next; /* nextp is in timebase units */ - /* Adjust timer */ timer_mod(timer, muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq)); }