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[201.69.66.211]) by smtp.gmail.com with ESMTPSA id i2-20020a4aab02000000b0055975f57993sm582564oon.42.2023.07.20.10.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 10:20:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.2 v5 08/11] target/riscv/cpu.c: add ADD_UNAVAIL_KVM_PROP_ARRAY() macro Date: Thu, 20 Jul 2023 14:19:30 -0300 Message-ID: <20230720171933.404398-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230720171933.404398-1-dbarboza@ventanamicro.com> References: <20230720171933.404398-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition, similar to what we're already doing with ADD_CPU_QDEV_PROPERTIES_ARRAY(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 23169a606f..8675839cb4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1900,6 +1900,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) NULL, (void *)prop_name); } +#define ADD_UNAVAIL_KVM_PROP_ARRAY(_obj, _array) \ + do { \ + for (int i = 0; i < ARRAY_SIZE(_array); i++) { \ + riscv_cpu_add_kvm_unavail_prop(_obj, _array[i].name); \ + } \ + } while (0) + static void riscv_cpu_add_kvm_properties(Object *obj) { DeviceState *dev = DEVICE(obj); @@ -1907,18 +1914,9 @@ static void riscv_cpu_add_kvm_properties(Object *obj) kvm_riscv_init_user_properties(obj); riscv_cpu_add_misa_properties(obj); - for (int i = 0; i < ARRAY_SIZE(riscv_cpu_extensions); i++) { - riscv_cpu_add_kvm_unavail_prop(obj, riscv_cpu_extensions[i].name); - } - - for (int i = 0; i < ARRAY_SIZE(riscv_cpu_vendor_exts); i++) { - riscv_cpu_add_kvm_unavail_prop(obj, riscv_cpu_vendor_exts[i].name); - } - - for (int i = 0; i < ARRAY_SIZE(riscv_cpu_experimental_exts); i++) { - riscv_cpu_add_kvm_unavail_prop(obj, - riscv_cpu_experimental_exts[i].name); - } + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions); + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_vendor_exts); + ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_experimental_exts); for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { /* Check if KVM created the property already */